entity.cpp

来自「这是一个介绍32位RISC处理器软核的设计与验证」· C++ 代码 · 共 47 行

////////////////////////////////////////////////////////////////////////////////
//   ____  ____   
//  /   /\/   /  
// /___/  \  /   
// \   \   \/  
//  \   \        Copyright (c) 2003-2004 Xilinx, Inc.
//  /   /        All Right Reserved. 
// /___/   /      
// \   \  /  \  
//  \___\/\___\
////////////////////////////////////////////////////////////////////////////////


#include "std/textio/textio.h"
#include "ieee/std_logic_textio/std_logic_textio.h"
#include "ieee/std_logic_unsigned/std_logic_unsigned.h"
#include "ieee/std_logic_arith/std_logic_arith.h"
#include "ieee/std_logic_1164/std_logic_1164.h"
#include "work/rcv_tbw/entity.h"

static const char *entFileName = "E:/vhdl/myproject/sent_receive/rcv_tbw.vhw";
#ifdef _MSC_VER
#pragma warning(disable: 4355)
#endif

Work_rcv_tbw::Work_rcv_tbw(const char *name, const char* ArchName, const char* fileName, int numOfLine): HSim__s6(false,name,"rcv_tbw", ArchName, fileName, HSim::VhdlDesignEntity, numOfLine + 6)

{
;
  SetPorts();
 
}

Work_rcv_tbw::~Work_rcv_tbw()
{
}

void Work_rcv_tbw::SetPorts()
{
}

void Work_rcv_tbw::constructEntityObject()
{
;
}