hdllib.ref

这是一个介绍32位RISC处理器软核的设计与验证

AR sent_receive_tbw testbench_arch E:/vhdl/myproject/sent_receive/sent_receive_tbw.vhw sub00/vhpl11 1207740909
AR fa_tbw testbench_arch E:/vhdl/myproject/sent_receive/fa_tbw.vhw sub00/vhpl03 1207738876
AR sent_receive_sch behavioral E:/vhdl/myproject/sent_receive/sent_receive_sch.vhf sub00/vhpl09 1207740907
EN rcv_tbw NULL E:/vhdl/myproject/sent_receive/rcv_tbw.vhw sub00/vhpl06 1207740758
EN sent_receive_tbw NULL E:/vhdl/myproject/sent_receive/sent_receive_tbw.vhw sub00/vhpl10 1207740908
AR rcv_v behavioral E:/vhdl/myproject/sent_receive/rcv_v.vhd sub00/vhpl05 1207731330
AR fa_v behavioral E:/vhdl/myproject/sent_receive/fa_v.vhd sub00/vhpl01 1207738874
AR rcv_tbw testbench_arch E:/vhdl/myproject/sent_receive/rcv_tbw.vhw sub00/vhpl07 1207740759
EN fa_tbw NULL E:/vhdl/myproject/sent_receive/fa_tbw.vhw sub00/vhpl02 1207738875
EN rcv_v NULL E:/vhdl/myproject/sent_receive/rcv_v.vhd sub00/vhpl04 1207731329
EN fa_v NULL E:/vhdl/myproject/sent_receive/fa_v.vhd sub00/vhpl00 1207738873
EN sent_receive_sch NULL E:/vhdl/myproject/sent_receive/sent_receive_sch.vhf sub00/vhpl08 1207740906