📄 e__xilinx_vhdl_mti_se_unisim__info
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dE:\Modeltech_6.2b\examplesFE:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L3686VeXjKni`__1UldILJSOP?21OE;C;6.2b;3531o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Aclk_div4r_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clk_div4r eXjKni`__1UldILJSOP?21l3704L3699VV6zz=UM]Le4@nbc2JRoT[0OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Eclk_div4rsdw1107957124DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dE:\Modeltech_6.2b\examplesFE:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L3791VcmRjQC[U2K`k7]S5@KWLV3OE;C;6.2b;3531o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Aclk_div4rsd_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clk_div4rsd cmRjQC[U2K`k7]S5@KWLV3l3809L3804VabaZ72R]FacPc]4MRdozb3OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Eclk_div4sdw1107957124DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dE:\Modeltech_6.2b\examplesFE:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L3902VPdL8[^558EcAO[BPb_H3n3OE;C;6.2b;3531o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Aclk_div4sd_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clk_div4sd PdL8[^558EcAO[BPb_H3n3l3918L3914V6zQ^Ji1;VXb@MT7FLT95Y1OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Eclk_div6w1107957124DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dE:\Modeltech_6.2b\examplesFE:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L3974VISXCiDD<j_gGigfZoi?Un0OE;C;6.2b;3531o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Aclk_div6_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clk_div6 ISXCiDD<j_gGigfZoi?Un0l3990L3986V9]i]3bgY98[OZPbMEg<O33OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Eclk_div6rw1107957124DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dE:\Modeltech_6.2b\examplesFE:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L4034V]GFfZUfRBMIP2NPB_Ka=?0OE;C;6.2b;3531o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Aclk_div6r_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clk_div6r ]GFfZUfRBMIP2NPB_Ka=?0l4051L4046VCYEaG^CDoHT1Hh[hf6<LX2OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Eclk_div6rsdw1107957124DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dE:\Modeltech_6.2b\examplesFE:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L4138V@`FTR_h?ZR<Z@:QkFWADD3OE;C;6.2b;3531o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Aclk_div6rsd_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clk_div6rsd @`FTR_h?ZR<Z@:QkFWADD3l4157L4152VmCHZZEc4Y9zJ0@0kcz<Lb1OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Eclk_div6sdw1107957124DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dE:\Modeltech_6.2b\examplesFE:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L4251VmidjBBo02X`]FX1>Mi0j<2OE;C;6.2b;3531o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Aclk_div6sd_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clk_div6sd midjBBo02X`]FX1>Mi0j<2l4268L4264V88Y>J>4^^zmKDHf134??f2OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Eclk_div8w1107957124DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dE:\Modeltech_6.2b\examplesFE:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L4324Vi<;n_[6K=nnCokEYIWj^Q1OE;C;6.2b;3531o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Aclk_div8_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clk_div8 i<;n_[6K=nnCokEYIWj^Q1l4340L4336VQaMZSDi[;]F0J4RbeYd=C1OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Eclk_div8rw1107957124DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dE:\Modeltech_6.2b\examplesFE:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L4384VzV5L6X5^^^X4FZI[WY6HS0OE;C;6.2b;3531o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Aclk_div8r_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clk_div8r zV5L6X5^^^X4FZI[WY6HS0l4402L4397VBCK8:Q;Gj0;GMRIzfeo`K1OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Eclk_div8rsdw1107957124DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dE:\Modeltech_6.2b\examplesFE:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L4489VYdFozmfbLo2lO@>f;8=dJ3OE;C;6.2b;3531o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Aclk_div8rsd_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clk_div8rsd YdFozmfbLo2lO@>f;8=dJ3l4508L4503VIOQOzM?S8GhCizhR`P=RB0OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Eclk_div8sdw1107957124DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dE:\Modeltech_6.2b\examplesFE:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L4601VjgSJ11ce8n_^UlJ@FecMo1OE;C;6.2b;3531o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Aclk_div8sd_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clk_div8sd jgSJ11ce8n_^UlJ@FecMo1l4617L4613Ve1k23@KMg<PK2I5_?43M?2OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Eclkdllw1107957124DP ieee vital_primitives E9g6AWKAc2T]enMfl94If3DP unisim vpkg F^fCCF2^cBPlHWmF419dn1DP std textio K]Z^fghZ6B=BjnK5NomDT3DP ieee vital_timing OBWK>;kUYmkG<OChK2lhV1DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dE:\Modeltech_6.2b\examplesFE:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L4734VST>BDS:J?P003MkTe_M5a2OE;C;6.2b;3531o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Aclkdll_vDP ieee vital_primitives E9g6AWKAc2T]enMfl94If3DP unisim vpkg F^fCCF2^cBPlHWmF419dn1DP std textio K]Z^fghZ6B=BjnK5NomDT3DP ieee vital_timing OBWK>;kUYmkG<OChK2lhV1DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clkdll ST>BDS:J?P003MkTe_M5a2l4833L4778V72MEP34U`flmZz6X1ZNgD1OE;C;6.2b;3531M5 ieee std_logic_1164M4 ieee vital_timingM3 std textioM2 unisim vpkgM1 ieee vital_primitiveso-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Eclkdll_maximum_period_checkw1107957124DP std textio K]Z^fghZ6B=BjnK5NomDT3DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dE:\Modeltech_6.2b\examplesFE:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L4674V]jAW]Y3A8oTZBiTlO^7gW2OE;C;6.2b;3531o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Aclkdll_maximum_period_check_vDP std textio K]Z^fghZ6B=BjnK5NomDT3DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clkdll_maximum_period_check ]jAW]Y3A8oTZBiTlO^7gW2l4686L4685VH[Tk2J8klH3nD@6mX>XE^0OE;C;6.2b;3531M2 ieee std_logic_1164M1 std textioo-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Eclkdllew1107957124DP ieee vital_primitives E9g6AWKAc2T]enMfl94If3DP unisim vpkg F^fCCF2^cBPlHWmF419dn1DP std textio K]Z^fghZ6B=BjnK5NomDT3DP ieee vital_timing OBWK>;kUYmkG<OChK2lhV1DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dE:\Modeltech_6.2b\examplesFE:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L5496VHPfJRc9_cK7h_=:[fSZkU0OE;C;6.2b;3531o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Aclkdlle_vDP ieee vital_primitives E9g6AWKAc2T]enMfl94If3DP unisim vpkg F^fCCF2^cBPlHWmF419dn1DP std textio K]Z^fghZ6B=BjnK5NomDT3DP ieee vital_timing OBWK>;kUYmkG<OChK2lhV1DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clkdlle HPfJRc9_cK7h_=:[fSZkU0l5596L5541VJ7U80?FmYE@i4heBV4?_D3OE;C;6.2b;3531M5 ieee std_logic_1164M4 ieee vital_timingM3 std textioM2 unisim vpkgM1 ieee vital_primitiveso-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Eclkdlle_maximum_period_checkw1107957124DP std textio K]Z^fghZ6B=BjnK5NomDT3DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dE:\Modeltech_6.2b\examplesFE:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L5436V^9A_IO[^@;KChz:JAHODn2OE;C;6.2b;3531o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Aclkdlle_maximum_period_check_vDP std textio K]Z^fghZ6B=BjnK5NomDT3DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clkdlle_maximum_period_check ^9A_IO[^@;KChz:JAHODn2l5448L5447VEb@@zmRCWA<gG01YiTimc1OE;C;6.2b;3531M2 ieee std_logic_1164M1 std textioo-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Eclkdllhfw1107957124DP ieee vital_primitives E9g6AWKAc2T]enMfl94If3DP unisim vpkg F^fCCF2^cBPlHWmF419dn1DP std textio K]Z^fghZ6B=BjnK5NomDT3DP ieee vital_timing OBWK>;kUYmkG<OChK2lhV1DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dE:\Modeltech_6.2b\examplesFE:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L6288VZE7;BFY_^RQY1TN`GCAYJ0OE;C;6.2b;3531o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Aclkdllhf_vDP ieee vital_primitives E9g6AWKAc2T]enMfl94If3DP unisim vpkg F^fCCF2^cBPlHWmF419dn1DP std textio K]Z^fghZ6B=BjnK5NomDT3DP ieee vital_timing OBWK>;kUYmkG<OChK2lhV1DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clkdllhf ZE7;BFY_^RQY1TN`GCAYJ0l6384L6329V382AZSfQEjFB2S6L3l5mb2OE;C;6.2b;3531M5 ieee std_logic_1164M4 ieee vital_timingM3 std textioM2 unisim vpkgM1 ieee vital_primitiveso-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Eclkdllhf_maximum_period_checkw1107957124DP std textio K]Z^fghZ6B=BjnK5NomDT3DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dE:\Modeltech_6.2b\examplesFE:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L6228V_8mlAZJ>3`KNf]COX2m>^1OE;C;6.2b;3531o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Aclkdllhf_maximum_period_check_vDP std textio K]Z^fghZ6B=BjnK5NomDT3DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clkdllhf_maximum_period_check _8mlAZJ>3`KNf]COX2m>^1l6240L6239V_ELi4ZS;?4oW:zX9]X[dB0OE;C;6.2b;3531M2 ieee std_logic_1164M1 std textioo-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Econfigw1107957124DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dE:\Modeltech_6.2b\examplesFE:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L6954VJEF@?NjAR8Z=?3oNAz4?f2OE;C;6.2b;3531o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Aconfig_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work config JEF@?NjAR8Z=?3oNAz4?f2l6958L6957Vgo4>DIWAnFcG^UBz]Z_<10OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Edcc_fpgacorew1107957122DP unisim vcomponents Mgc?1DO:gobG6MeLhjRoA1DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dE:\Modeltech_6.2b\examplesFE:\Xilinx\vhdl\src\unisims\unisim_SMODEL.vhdl0L27VGPlmZaUo@UFT=Q0IRRZd`2OE;C;6.2b;3531o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Adcc_fpgacore_vDP unisim vcomponents Mgc?1DO:gobG6MeLhjRoA1DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work dcc_fpgacore GPlmZaUo@UFT=Q0IRRZd`2l116L72VC2BY4z2?Jg@gj7emzchDO3OE;C;6.2b;3531M2 ieee std_logic_1164M1 unisim vcomponentso-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Edcc_fpgacore_swiftw1107958380DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dE:\Modeltech_6.2b\examplesFE:\Xilinx\smartmodel\nt\wrappers\mtivhdl\smartmodel_wrappers.vhdl0L3Vhbo5<@A<glfHAAD?I=<292OE;C;6.2b;3531o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1AsmartmodelDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work dcc_fpgacore_swift hbo5<@A<glfHAAD?I=<292l56L53VFVnBOD6HBiY^Xh8RYMJSg2OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Edcc_fpgacore_swift_busw1107958380DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dE:\Modeltech_6.2b\examplesFE:\Xilinx\smartmodel\nt\wrappers\mtivhdl\smartmodel_wrappers.vhdl0L5718Vdda^_`?WPUAYH;dmZ3BG=3OE;C;6.2b;3531o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Adcc_fpgacore_swift_bus_vDE work dcc_fpgacore_swift hbo5<@A<glfHAAD?I=<292DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work dcc_fpgacore_swift_bus dda^_`?WPUAYH;dmZ3BG=3l5859L5761VKPmee0E<4iAaChFH84eOB3OE;C;6.2b;3531M2 ieee std_logic_1164M1 ieee numeric_stdo-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Edciresetw1107957124DP ieee vital_primitives E9g6AWKAc2T]enMfl94If3DP ieee vital_timing OBWK>;kUYmkG<OChK2lhV1DP std textio K]Z^fghZ6B=BjnK5NomDT3DP unisim vpkg F^fCCF2^cBPlHWmF419dn1DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dE:\Modeltech_6.2b\examplesFE:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L131472VBzYCJ0:i<<VOlbg56<=VJ1OE;C;6.2b;3531o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Adcireset_vDP ieee vital_primitives E9g6AWKAc2T]enMfl94If3DP ieee vital_timing OBWK>;kUYmkG<OChK2lhV1DP std textio K]Z^fghZ6B=BjnK5NomDT3DP unisim vpkg F^fCCF2^cBPlHWmF419dn1DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work dcireset BzYCJ0:i<<VOlbg56<=VJ1l131484L131482Vgj[_=kRz]SozU9A_ejo9i3OE;C;6.2b;3531M5 ieee std_logic_1164M4 unisim vpkgM3 std textioM2 ieee vital_timingM1 ieee vital_primitiveso-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Edcmw1107957124DP ieee vital_primitives E9g6AWKAc2T]enMfl94If3DP unisim vpkg F^fCCF2^cBPlHWmF419dn1DP std textio K]Z^fghZ6B=BjnK5NomDT3DP ieee vital_timing OBWK>;kUYmkG<OChK2lhV1DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dE:\Modeltech_6.2b\examplesFE:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L7231V[jan90mlMfz_kTlPg=?fz2OE;C;6.2b;3531o-source -93 -work E:\Xilinx\vhdl\mti_se\unisimtExplicit 1Adcm_vDP ieee vital_primitives E9g6AWKAc2T]enMfl94If3DP unisim vpkg F^fCCF2^cBPlHWmF419dn1DP std textio K]Z^fghZ6B=BjnK5NomDT3DP ieee vital_timing OBWK>;kUYmkG<OChK2lhV1⌨️ 快捷键说明
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