📄 k60-keil
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#define AIPS_PACRH_TP7_SHIFT 0
#define AIPS_PACRH_WP7_MASK 0x2u
#define AIPS_PACRH_WP7_SHIFT 1
#define AIPS_PACRH_SP7_MASK 0x4u
#define AIPS_PACRH_SP7_SHIFT 2
#define AIPS_PACRH_TP6_MASK 0x10u
#define AIPS_PACRH_TP6_SHIFT 4
#define AIPS_PACRH_WP6_MASK 0x20u
#define AIPS_PACRH_WP6_SHIFT 5
#define AIPS_PACRH_SP6_MASK 0x40u
#define AIPS_PACRH_SP6_SHIFT 6
#define AIPS_PACRH_TP5_MASK 0x100u
#define AIPS_PACRH_TP5_SHIFT 8
#define AIPS_PACRH_WP5_MASK 0x200u
#define AIPS_PACRH_WP5_SHIFT 9
#define AIPS_PACRH_SP5_MASK 0x400u
#define AIPS_PACRH_SP5_SHIFT 10
#define AIPS_PACRH_TP4_MASK 0x1000u
#define AIPS_PACRH_TP4_SHIFT 12
#define AIPS_PACRH_WP4_MASK 0x2000u
#define AIPS_PACRH_WP4_SHIFT 13
#define AIPS_PACRH_SP4_MASK 0x4000u
#define AIPS_PACRH_SP4_SHIFT 14
#define AIPS_PACRH_TP3_MASK 0x10000u
#define AIPS_PACRH_TP3_SHIFT 16
#define AIPS_PACRH_WP3_MASK 0x20000u
#define AIPS_PACRH_WP3_SHIFT 17
#define AIPS_PACRH_SP3_MASK 0x40000u
#define AIPS_PACRH_SP3_SHIFT 18
#define AIPS_PACRH_TP2_MASK 0x100000u
#define AIPS_PACRH_TP2_SHIFT 20
#define AIPS_PACRH_WP2_MASK 0x200000u
#define AIPS_PACRH_WP2_SHIFT 21
#define AIPS_PACRH_SP2_MASK 0x400000u
#define AIPS_PACRH_SP2_SHIFT 22
#define AIPS_PACRH_TP1_MASK 0x1000000u
#define AIPS_PACRH_TP1_SHIFT 24
#define AIPS_PACRH_WP1_MASK 0x2000000u
#define AIPS_PACRH_WP1_SHIFT 25
#define AIPS_PACRH_SP1_MASK 0x4000000u
#define AIPS_PACRH_SP1_SHIFT 26
#define AIPS_PACRH_TP0_MASK 0x10000000u
#define AIPS_PACRH_TP0_SHIFT 28
#define AIPS_PACRH_WP0_MASK 0x20000000u
#define AIPS_PACRH_WP0_SHIFT 29
#define AIPS_PACRH_SP0_MASK 0x40000000u
#define AIPS_PACRH_SP0_SHIFT 30
/* PACRI Bit Fields */
#define AIPS_PACRI_TP7_MASK 0x1u
#define AIPS_PACRI_TP7_SHIFT 0
#define AIPS_PACRI_WP7_MASK 0x2u
#define AIPS_PACRI_WP7_SHIFT 1
#define AIPS_PACRI_SP7_MASK 0x4u
#define AIPS_PACRI_SP7_SHIFT 2
#define AIPS_PACRI_TP6_MASK 0x10u
#define AIPS_PACRI_TP6_SHIFT 4
#define AIPS_PACRI_WP6_MASK 0x20u
#define AIPS_PACRI_WP6_SHIFT 5
#define AIPS_PACRI_SP6_MASK 0x40u
#define AIPS_PACRI_SP6_SHIFT 6
#define AIPS_PACRI_TP5_MASK 0x100u
#define AIPS_PACRI_TP5_SHIFT 8
#define AIPS_PACRI_WP5_MASK 0x200u
#define AIPS_PACRI_WP5_SHIFT 9
#define AIPS_PACRI_SP5_MASK 0x400u
#define AIPS_PACRI_SP5_SHIFT 10
#define AIPS_PACRI_TP4_MASK 0x1000u
#define AIPS_PACRI_TP4_SHIFT 12
#define AIPS_PACRI_WP4_MASK 0x2000u
#define AIPS_PACRI_WP4_SHIFT 13
#define AIPS_PACRI_SP4_MASK 0x4000u
#define AIPS_PACRI_SP4_SHIFT 14
#define AIPS_PACRI_TP3_MASK 0x10000u
#define AIPS_PACRI_TP3_SHIFT 16
#define AIPS_PACRI_WP3_MASK 0x20000u
#define AIPS_PACRI_WP3_SHIFT 17
#define AIPS_PACRI_SP3_MASK 0x40000u
#define AIPS_PACRI_SP3_SHIFT 18
#define AIPS_PACRI_TP2_MASK 0x100000u
#define AIPS_PACRI_TP2_SHIFT 20
#define AIPS_PACRI_WP2_MASK 0x200000u
#define AIPS_PACRI_WP2_SHIFT 21
#define AIPS_PACRI_SP2_MASK 0x400000u
#define AIPS_PACRI_SP2_SHIFT 22
#define AIPS_PACRI_TP1_MASK 0x1000000u
#define AIPS_PACRI_TP1_SHIFT 24
#define AIPS_PACRI_WP1_MASK 0x2000000u
#define AIPS_PACRI_WP1_SHIFT 25
#define AIPS_PACRI_SP1_MASK 0x4000000u
#define AIPS_PACRI_SP1_SHIFT 26
#define AIPS_PACRI_TP0_MASK 0x10000000u
#define AIPS_PACRI_TP0_SHIFT 28
#define AIPS_PACRI_WP0_MASK 0x20000000u
#define AIPS_PACRI_WP0_SHIFT 29
#define AIPS_PACRI_SP0_MASK 0x40000000u
#define AIPS_PACRI_SP0_SHIFT 30
/* PACRJ Bit Fields */
#define AIPS_PACRJ_TP7_MASK 0x1u
#define AIPS_PACRJ_TP7_SHIFT 0
#define AIPS_PACRJ_WP7_MASK 0x2u
#define AIPS_PACRJ_WP7_SHIFT 1
#define AIPS_PACRJ_SP7_MASK 0x4u
#define AIPS_PACRJ_SP7_SHIFT 2
#define AIPS_PACRJ_TP6_MASK 0x10u
#define AIPS_PACRJ_TP6_SHIFT 4
#define AIPS_PACRJ_WP6_MASK 0x20u
#define AIPS_PACRJ_WP6_SHIFT 5
#define AIPS_PACRJ_SP6_MASK 0x40u
#define AIPS_PACRJ_SP6_SHIFT 6
#define AIPS_PACRJ_TP5_MASK 0x100u
#define AIPS_PACRJ_TP5_SHIFT 8
#define AIPS_PACRJ_WP5_MASK 0x200u
#define AIPS_PACRJ_WP5_SHIFT 9
#define AIPS_PACRJ_SP5_MASK 0x400u
#define AIPS_PACRJ_SP5_SHIFT 10
#define AIPS_PACRJ_TP4_MASK 0x1000u
#define AIPS_PACRJ_TP4_SHIFT 12
#define AIPS_PACRJ_WP4_MASK 0x2000u
#define AIPS_PACRJ_WP4_SHIFT 13
#define AIPS_PACRJ_SP4_MASK 0x4000u
#define AIPS_PACRJ_SP4_SHIFT 14
#define AIPS_PACRJ_TP3_MASK 0x10000u
#define AIPS_PACRJ_TP3_SHIFT 16
#define AIPS_PACRJ_WP3_MASK 0x20000u
#define AIPS_PACRJ_WP3_SHIFT 17
#define AIPS_PACRJ_SP3_MASK 0x40000u
#define AIPS_PACRJ_SP3_SHIFT 18
#define AIPS_PACRJ_TP2_MASK 0x100000u
#define AIPS_PACRJ_TP2_SHIFT 20
#define AIPS_PACRJ_WP2_MASK 0x200000u
#define AIPS_PACRJ_WP2_SHIFT 21
#define AIPS_PACRJ_SP2_MASK 0x400000u
#define AIPS_PACRJ_SP2_SHIFT 22
#define AIPS_PACRJ_TP1_MASK 0x1000000u
#define AIPS_PACRJ_TP1_SHIFT 24
#define AIPS_PACRJ_WP1_MASK 0x2000000u
#define AIPS_PACRJ_WP1_SHIFT 25
#define AIPS_PACRJ_SP1_MASK 0x4000000u
#define AIPS_PACRJ_SP1_SHIFT 26
#define AIPS_PACRJ_TP0_MASK 0x10000000u
#define AIPS_PACRJ_TP0_SHIFT 28
#define AIPS_PACRJ_WP0_MASK 0x20000000u
#define AIPS_PACRJ_WP0_SHIFT 29
#define AIPS_PACRJ_SP0_MASK 0x40000000u
#define AIPS_PACRJ_SP0_SHIFT 30
/* PACRK Bit Fields */
#define AIPS_PACRK_TP7_MASK 0x1u
#define AIPS_PACRK_TP7_SHIFT 0
#define AIPS_PACRK_WP7_MASK 0x2u
#define AIPS_PACRK_WP7_SHIFT 1
#define AIPS_PACRK_SP7_MASK 0x4u
#define AIPS_PACRK_SP7_SHIFT 2
#define AIPS_PACRK_TP6_MASK 0x10u
#define AIPS_PACRK_TP6_SHIFT 4
#define AIPS_PACRK_WP6_MASK 0x20u
#define AIPS_PACRK_WP6_SHIFT 5
#define AIPS_PACRK_SP6_MASK 0x40u
#define AIPS_PACRK_SP6_SHIFT 6
#define AIPS_PACRK_TP5_MASK 0x100u
#define AIPS_PACRK_TP5_SHIFT 8
#define AIPS_PACRK_WP5_MASK 0x200u
#define AIPS_PACRK_WP5_SHIFT 9
#define AIPS_PACRK_SP5_MASK 0x400u
#define AIPS_PACRK_SP5_SHIFT 10
#define AIPS_PACRK_TP4_MASK 0x1000u
#define AIPS_PACRK_TP4_SHIFT 12
#define AIPS_PACRK_WP4_MASK 0x2000u
#define AIPS_PACRK_WP4_SHIFT 13
#define AIPS_PACRK_SP4_MASK 0x4000u
#define AIPS_PACRK_SP4_SHIFT 14
#define AIPS_PACRK_TP3_MASK 0x10000u
#define AIPS_PACRK_TP3_SHIFT 16
#define AIPS_PACRK_WP3_MASK 0x20000u
#define AIPS_PACRK_WP3_SHIFT 17
#define AIPS_PACRK_SP3_MASK 0x40000u
#define AIPS_PACRK_SP3_SHIFT 18
#define AIPS_PACRK_TP2_MASK 0x100000u
#define AIPS_PACRK_TP2_SHIFT 20
#define AIPS_PACRK_WP2_MASK 0x200000u
#define AIPS_PACRK_WP2_SHIFT 21
#define AIPS_PACRK_SP2_MASK 0x400000u
#define AIPS_PACRK_SP2_SHIFT 22
#define AIPS_PACRK_TP1_MASK 0x1000000u
#define AIPS_PACRK_TP1_SHIFT 24
#define AIPS_PACRK_WP1_MASK 0x2000000u
#define AIPS_PACRK_WP1_SHIFT 25
#define AIPS_PACRK_SP1_MASK 0x4000000u
#define AIPS_PACRK_SP1_SHIFT 26
#define AIPS_PACRK_TP0_MASK 0x10000000u
#define AIPS_PACRK_TP0_SHIFT 28
#define AIPS_PACRK_WP0_MASK 0x20000000u
#define AIPS_PACRK_WP0_SHIFT 29
#define AIPS_PACRK_SP0_MASK 0x40000000u
#define AIPS_PACRK_SP0_SHIFT 30
/* PACRL Bit Fields */
#define AIPS_PACRL_TP7_MASK 0x1u
#define AIPS_PACRL_TP7_SHIFT 0
#define AIPS_PACRL_WP7_MASK 0x2u
#define AIPS_PACRL_WP7_SHIFT 1
#define AIPS_PACRL_SP7_MASK 0x4u
#define AIPS_PACRL_SP7_SHIFT 2
#define AIPS_PACRL_TP6_MASK 0x10u
#define AIPS_PACRL_TP6_SHIFT 4
#define AIPS_PACRL_WP6_MASK 0x20u
#define AIPS_PACRL_WP6_SHIFT 5
#define AIPS_PACRL_SP6_MASK 0x40u
#define AIPS_PACRL_SP6_SHIFT 6
#define AIPS_PACRL_TP5_MASK 0x100u
#define AIPS_PACRL_TP5_SHIFT 8
#define AIPS_PACRL_WP5_MASK 0x200u
#define AIPS_PACRL_WP5_SHIFT 9
#define AIPS_PACRL_SP5_MASK 0x400u
#define AIPS_PACRL_SP5_SHIFT 10
#define AIPS_PACRL_TP4_MASK 0x1000u
#define AIPS_PACRL_TP4_SHIFT 12
#define AIPS_PACRL_WP4_MASK 0x2000u
#define AIPS_PACRL_WP4_SHIFT 13
#define AIPS_PACRL_SP4_MASK 0x4000u
#define AIPS_PACRL_SP4_SHIFT 14
#define AIPS_PACRL_TP3_MASK 0x10000u
#define AIPS_PACRL_TP3_SHIFT 16
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