📄 infones_mapper.cpp
字号:
InfoNES_Mirroring( 3 );
}
}
}
break;
case 1:
{
BYTE byBankNum = Map1_Regs[1];
if ( Map1_Size == Map1_1024K )
{
if ( Map1_Regs[0] & 0x10 )
{
if ( Map1_swap )
{
Map1_256K_base = (Map1_Regs[1] & 0x10) >> 4;
if(Map1_Regs[0] & 0x08)
{
Map1_256K_base |= ((Map1_Regs[2] & 0x10) >> 3);
}
Map1_set_ROM_banks();
Map1_swap = 0;
}
else
{
Map1_swap = 1;
}
}
else
{
// use 1st or 4th 256K banks
Map1_256K_base = ( Map1_Regs[1] & 0x10 ) ? 3 : 0;
Map1_set_ROM_banks();
}
}
else if((Map1_Size == Map1_512K) && (!NesHeader.byVRomSize))
{
Map1_256K_base = (Map1_Regs[1] & 0x10) >> 4;
Map1_set_ROM_banks();
}
else if ( NesHeader.byVRomSize )
{
// set VROM bank at $0000
if ( Map1_Regs[0] & 0x10 )
{
// swap 4K
byBankNum <<= 2;
PPUBANK[ 0 ] = VROMPAGE( (byBankNum+0) % (NesHeader.byVRomSize << 3) );
PPUBANK[ 1 ] = VROMPAGE( (byBankNum+1) % (NesHeader.byVRomSize << 3) );
PPUBANK[ 2 ] = VROMPAGE( (byBankNum+2) % (NesHeader.byVRomSize << 3) );
PPUBANK[ 3 ] = VROMPAGE( (byBankNum+3) % (NesHeader.byVRomSize << 3) );
InfoNES_SetupChr();
}
else
{
// swap 8K
byBankNum <<= 2;
PPUBANK[ 0 ] = VROMPAGE( (byBankNum+0) % (NesHeader.byVRomSize << 3) );
PPUBANK[ 1 ] = VROMPAGE( (byBankNum+1) % (NesHeader.byVRomSize << 3) );
PPUBANK[ 2 ] = VROMPAGE( (byBankNum+2) % (NesHeader.byVRomSize << 3) );
PPUBANK[ 3 ] = VROMPAGE( (byBankNum+3) % (NesHeader.byVRomSize << 3) );
PPUBANK[ 4 ] = VROMPAGE( (byBankNum+4) % (NesHeader.byVRomSize << 3) );
PPUBANK[ 5 ] = VROMPAGE( (byBankNum+5) % (NesHeader.byVRomSize << 3) );
PPUBANK[ 6 ] = VROMPAGE( (byBankNum+6) % (NesHeader.byVRomSize << 3) );
PPUBANK[ 7 ] = VROMPAGE( (byBankNum+7) % (NesHeader.byVRomSize << 3) );
InfoNES_SetupChr();
}
}
}
break;
case 2:
{
BYTE byBankNum = Map1_Regs[2];
if((Map1_Size == Map1_1024K) && (Map1_Regs[0] & 0x08))
{
if(Map1_swap)
{
Map1_256K_base = (Map1_Regs[1] & 0x10) >> 4;
Map1_256K_base |= ((Map1_Regs[2] & 0x10) >> 3);
Map1_set_ROM_banks();
Map1_swap = 0;
}
else
{
Map1_swap = 1;
}
}
if(!NesHeader.byVRomSize)
{
if ( Map1_Regs[ 0 ] & 0x10 )
{
byBankNum <<= 2;
PPUBANK[ 4 ] = VRAMPAGE0( byBankNum+0 );
PPUBANK[ 5 ] = VRAMPAGE0( byBankNum+1 );
PPUBANK[ 6 ] = VRAMPAGE0( byBankNum+2 );
PPUBANK[ 7 ] = VRAMPAGE0( byBankNum+3 );
InfoNES_SetupChr();
break;
}
}
// set 4K VROM bank at $1000
if(Map1_Regs[0] & 0x10)
{
// swap 4K
byBankNum <<= 2;
PPUBANK[ 4 ] = VROMPAGE( (byBankNum+0) % (NesHeader.byVRomSize << 3) );
PPUBANK[ 5 ] = VROMPAGE( (byBankNum+1) % (NesHeader.byVRomSize << 3) );
PPUBANK[ 6 ] = VROMPAGE( (byBankNum+2) % (NesHeader.byVRomSize << 3) );
PPUBANK[ 7 ] = VROMPAGE( (byBankNum+3) % (NesHeader.byVRomSize << 3) );
InfoNES_SetupChr();
}
}
break;
case 3:
{
BYTE byBankNum = Map1_Regs[3];
// set ROM bank
if ( Map1_Regs[0] & 0x08 )
{
// 16K of ROM
byBankNum <<= 1;
if ( Map1_Regs[0] & 0x04 )
{
// 16K of ROM at $8000
Map1_bank1 = byBankNum;
Map1_bank2 = byBankNum+1;
Map1_bank3 = Map1_HI1;
Map1_bank4 = Map1_HI2;
}
else
{
// 16K of ROM at $C000
if(Map1_Size == Map1_SMALL)
{
Map1_bank1 = 0;
Map1_bank2 = 1;
Map1_bank3 = byBankNum;
Map1_bank4 = byBankNum+1;
}
}
}
else
{
// 32K of ROM at $8000
byBankNum <<= 1;
Map1_bank1 = byBankNum;
Map1_bank2 = byBankNum+1;
if(Map1_Size == Map1_SMALL)
{
Map1_bank3 = byBankNum+2;
Map1_bank4 = byBankNum+3;
}
}
Map1_set_ROM_banks();
}
break;
}
}
/*===================================================================*/
/* */
/* Mapper 2 (UNROM) */
/* */
/*===================================================================*/
/*-------------------------------------------------------------------*/
/* Initialize Mapper 2 */
/*-------------------------------------------------------------------*/
void Map2_Init()
{
/* Initialize Mapper */
MapperInit = Map2_Init;
/* Write to Mapper */
MapperWrite = Map2_Write;
/* Write to SRAM */
MapperSram = Map0_Sram;
/* Write to APU */
MapperApu = Map0_Apu;
/* Read from APU */
MapperReadApu = Map0_ReadApu;
/* Callback at VSync */
MapperVSync = Map0_VSync;
/* Callback at HSync */
MapperHSync = Map0_HSync;
/* Callback at PPU */
MapperPPU = Map0_PPU;
/* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */
MapperRenderScreen = Map0_RenderScreen;
/* Set SRAM Banks */
SRAMBANK = SRAM;
/* Set ROM Banks */
ROMBANK0 = ROMPAGE( 0 );
ROMBANK1 = ROMPAGE( 1 );
ROMBANK2 = ROMLASTPAGE( 1 );
ROMBANK3 = ROMLASTPAGE( 0 );
/* Set up wiring of the interrupt pin */
K6502_Set_Int_Wiring( 1, 1 );
}
/*-------------------------------------------------------------------*/
/* Mapper 2 Write Function */
/*-------------------------------------------------------------------*/
void Map2_Write( WORD wAddr, BYTE byData )
{
/* Set ROM Banks */
byData %= NesHeader.byRomSize;
byData <<= 1;
ROMBANK0 = ROMPAGE( byData );
ROMBANK1 = ROMPAGE( byData + 1 );
}
/*===================================================================*/
/* */
/* Mapper 3 (VROM Switch) */
/* */
/*===================================================================*/
/*-------------------------------------------------------------------*/
/* Initialize Mapper 3 */
/*-------------------------------------------------------------------*/
void Map3_Init()
{
int nPage;
/* Initialize Mapper */
MapperInit = Map3_Init;
/* Write to Mapper */
MapperWrite = Map3_Write;
/* Write to SRAM */
MapperSram = Map0_Sram;
/* Write to APU */
MapperApu = Map0_Apu;
/* Read from APU */
MapperReadApu = Map0_ReadApu;
/* Callback at VSync */
MapperVSync = Map0_VSync;
/* Callback at HSync */
MapperHSync = Map0_HSync;
/* Callback at PPU */
MapperPPU = Map0_PPU;
/* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */
MapperRenderScreen = Map0_RenderScreen;
/* Set SRAM Banks */
SRAMBANK = SRAM;
/* Set ROM Banks */
if ( ( NesHeader.byRomSize << 1 ) > 2 )
{
ROMBANK0 = ROMPAGE( 0 );
ROMBANK1 = ROMPAGE( 1 );
ROMBANK2 = ROMPAGE( 2 );
ROMBANK3 = ROMPAGE( 3 );
} else {
ROMBANK0 = ROMPAGE( 0 );
ROMBANK1 = ROMPAGE( 1 );
ROMBANK2 = ROMPAGE( 0 );
ROMBANK3 = ROMPAGE( 1 );
}
/* Set PPU Banks */
if ( NesHeader.byVRomSize > 0 )
{
for ( nPage = 0; nPage < 8; ++nPage )
{
PPUBANK[ nPage ] = VROMPAGE( nPage );
}
InfoNES_SetupChr();
}
/* Set up wiring of the interrupt pin */
/* "DragonQuest" doesn't run if IRQ isn't made to occur in CLI */
K6502_Set_Int_Wiring( 1, 1 );
}
/*-------------------------------------------------------------------*/
/* Mapper 3 Write Function */
/*-------------------------------------------------------------------*/
void Map3_Write( WORD wAddr, BYTE byData )
{
DWORD dwBase;
/* Set PPU Banks */
byData %= NesHeader.byVRomSize;
dwBase = ( (DWORD)byData ) << 3;
PPUBANK[ 0 ] = VROMPAGE( dwBase + 0 );
PPUBANK[ 1 ] = VROMPAGE( dwBase + 1 );
PPUBANK[ 2 ] = VROMPAGE( dwBase + 2 );
PPUBANK[ 3 ] = VROMPAGE( dwBase + 3 );
PPUBANK[ 4 ] = VROMPAGE( dwBase + 4 );
PPUBANK[ 5 ] = VROMPAGE( dwBase + 5 );
PPUBANK[ 6 ] = VROMPAGE( dwBase + 6 );
PPUBANK[ 7 ] = VROMPAGE( dwBase + 7 );
InfoNES_SetupChr();
}
/*===================================================================*/
/* */
/* Mapper 4 (MMC3) */
/* */
/*===================================================================*/
BYTE Map4_Regs[ 8 ];
DWORD Map4_Rom_Bank;
DWORD Map4_Prg0, Map4_Prg1;
DWORD Map4_Chr01, Map4_Chr23;
DWORD Map4_Chr4, Map4_Chr5, Map4_Chr6, Map4_Chr7;
#define Map4_Chr_Swap() ( Map4_Regs[ 0 ] & 0x80 )
#define Map4_Prg_Swap() ( Map4_Regs[ 0 ] & 0x40 )
BYTE Map4_IRQ_Enable;
BYTE Map4_IRQ_Cnt;
BYTE Map4_IRQ_Latch;
/*-------------------------------------------------------------------*/
/* Initialize Mapper 4 */
/*-------------------------------------------------------------------*/
void Map4_Init()
{
/* Initialize Mapper */
MapperInit = Map4_Init;
/* Write to Mapper */
MapperWrite = Map4_Write;
/* Write to SRAM */
MapperSram = Map0_Sram;
/* Write to APU */
MapperApu = Map0_Apu;
/* Read from APU */
MapperReadApu = Map0_ReadApu;
/* Callback at VSync */
MapperVSync = Map0_VSync;
/* Callback at HSync */
MapperHSync = Map4_HSync;
/* Callback at PPU */
MapperPPU = Map0_PPU;
/* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */
MapperRenderScreen = Map0_RenderScreen;
/* Set SRAM Banks */
SRAMBANK = SRAM;
/* Initialize State Registers */
for ( int nPage = 0; nPage < 8; nPage++ )
{
Map4_Regs[ nPage ] = 0x00;
}
/* Set ROM Banks */
Map4_Prg0 = 0;
Map4_Prg1 = 1;
Map4_Set_CPU_Banks();
/* Set PPU Banks */
if ( NesHeader.byVRomSize > 0 )
{
Map4_Chr01 = 0;
Map4_Chr23 = 2;
Map4_Chr4 = 4;
Map4_Chr5 = 5;
Map4_Chr6 = 6;
Map4_Chr7 = 7;
Map4_Set_PPU_Banks();
} else {
Map4_Chr01 = Map4_Chr23 = 0;
Map4_Chr4 = Map4_Chr5 = Map4_Chr6 = Map4_Chr7 = 0;
}
/* Initialize IRQ Registers */
Map4_IRQ_Enable = 0;
Map4_IRQ_Cnt = 0;
Map4_IRQ_Latch = 0;
/* Set up wiring of the interrupt pin */
K6502_Set_Int_Wiring( 1, 1 );
}
/*-------------------------------------------------------------------*/
/* Mapper 4 Write Function */
/*-------------------------------------------------------------------*/
void Map4_Write( WORD wAddr, BYTE byData )
{
DWORD dwBankNum;
switch ( wAddr & 0xe001 )
{
case 0x8000:
Map4_Regs[ 0 ] = byData;
Map4_Set_PPU_Banks();
Map4_Set_CPU_Banks();
break;
case 0x8001:
Map4_Regs[ 1 ] = byData;
dwBankNum = Map4_Regs[ 1 ];
switch ( Map4_Regs[ 0 ] & 0x07 )
{
/* Set PPU Banks */
case 0x00:
if ( NesHeader.byVRomSize > 0 )
{
dwBankNum &= 0xfe;
Map4_Chr01 = dwBankNum;
Map4_Set_PPU_Banks();
}
break;
case 0x01:
if ( NesHeader.byVRomSize > 0 )
{
dwBankNum &= 0xfe;
Map4_Chr23 = dwBankNum;
Map4_Set_PPU_Banks();
}
break;
case 0x02:
if ( NesHeader.byVRomSize > 0 )
{
Map4_Chr4 = dwBankNum;
Map4_Set_PPU_Banks();
}
break;
case 0x03:
if ( NesHeader.byVRomSize > 0 )
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