📄 infones_mapper.cpp
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/*===================================================================*/
/* */
/* InfoNES_Mapper.cpp : InfoNES Mapper Function */
/* */
/* 2000/05/16 InfoNES Project ( based on NesterJ and pNesX ) */
/* */
/*===================================================================*/
/*-------------------------------------------------------------------*/
/* Include files */
/*-------------------------------------------------------------------*/
#include "InfoNES.h"
#include "InfoNES_System.h"
#include "InfoNES_Mapper.h"
#include "K6502.h"
/*-------------------------------------------------------------------*/
/* Table of Mapper initialize function */
/*-------------------------------------------------------------------*/
struct MapperTable_tag MapperTable[] =
{
{ 0, Map0_Init },
{ 1, Map1_Init },
{ 2, Map2_Init },
{ 3, Map3_Init },
{ 4, Map4_Init },
{ 5, Map5_Init },
{ 6, Map6_Init },
{ 7, Map7_Init },
{ 8, Map8_Init },
{ 9, Map9_Init },
{ 10, Map10_Init },
{ 11, Map11_Init },
{ 15, Map15_Init },
{ 16, Map16_Init },
{ 17, Map17_Init },
{ 18, Map18_Init },
{ 19, Map19_Init },
{ 21, Map21_Init },
{ 22, Map22_Init },
{ 23, Map23_Init },
{ 24, Map24_Init },
{ 25, Map25_Init },
{ 26, Map26_Init },
{ 32, Map32_Init },
{ 33, Map33_Init },
{ 34, Map34_Init },
{ 40, Map40_Init },
{ 41, Map41_Init },
{ 42, Map42_Init },
{ 44, Map44_Init },
{ 46, Map46_Init },
{ 47, Map47_Init },
{ 48, Map48_Init },
{ 49, Map49_Init },
{ 50, Map50_Init },
{ 64, Map64_Init },
{ 65, Map65_Init },
{ 66, Map66_Init },
{ 67, Map67_Init },
{ 68, Map68_Init },
{ 69, Map69_Init },
{ 70, Map70_Init },
{ 71, Map71_Init },
{ 72, Map72_Init },
{ 73, Map73_Init },
{ 75, Map75_Init },
{ 76, Map76_Init },
{ 77, Map77_Init },
{ 78, Map78_Init },
{ 79, Map79_Init },
{ 80, Map80_Init },
{ 82, Map82_Init },
{ 83, Map83_Init },
{ 85, Map85_Init },
{ 86, Map86_Init },
{ 87, Map87_Init },
{ 88, Map88_Init },
{ 89, Map89_Init },
{ 90, Map90_Init },
{ 91, Map91_Init },
{ 92, Map92_Init },
{ 93, Map93_Init },
{ 94, Map94_Init },
{ 95, Map95_Init },
{ 97, Map97_Init },
{ 101, Map101_Init },
{ 112, Map112_Init },
{ 113, Map113_Init },
{ 114, Map114_Init },
{ 117, Map117_Init },
{ 118, Map118_Init },
{ 122, Map122_Init },
{ 151, Map151_Init },
{ 160, Map160_Init },
{ 180, Map180_Init },
{ 182, Map182_Init },
{ 185, Map185_Init },
{ 188, Map188_Init },
{ 189, Map189_Init },
{ 243, Map243_Init },
{ -1, NULL }
};
/*===================================================================*/
/* */
/* Mapper 0 */
/* */
/*===================================================================*/
/*-------------------------------------------------------------------*/
/* Initialize Mapper 0 */
/*-------------------------------------------------------------------*/
void Map0_Init()
{
/* Initialize Mapper */
MapperInit = Map0_Init;
/* Write to Mapper */
MapperWrite = Map0_Write;
/* Write to SRAM */
MapperSram = Map0_Sram;
/* Write to APU */
MapperApu = Map0_Apu;
/* Read from APU */
MapperReadApu = Map0_ReadApu;
/* Callback at VSync */
MapperVSync = Map0_VSync;
/* Callback at HSync */
MapperHSync = Map0_HSync;
/* Callback at PPU */
MapperPPU = Map0_PPU;
/* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */
MapperRenderScreen = Map0_RenderScreen;
/* Set ROM Banks */
if ( NesHeader.byRomSize > 1 )
{
ROMBANK0 = ROMPAGE( 0 );
ROMBANK1 = ROMPAGE( 1 );
ROMBANK2 = ROMPAGE( 2 );
ROMBANK3 = ROMPAGE( 3 );
}
else if ( NesHeader.byRomSize > 0 )
{
ROMBANK0 = ROMPAGE( 0 );
ROMBANK1 = ROMPAGE( 1 );
ROMBANK2 = ROMPAGE( 0 );
ROMBANK3 = ROMPAGE( 1 );
} else {
ROMBANK0 = ROMPAGE( 0 );
ROMBANK1 = ROMPAGE( 0 );
ROMBANK2 = ROMPAGE( 0 );
ROMBANK3 = ROMPAGE( 0 );
}
/* Set PPU Banks */
if ( NesHeader.byVRomSize > 0 )
{
for ( int nPage = 0; nPage < 8; ++nPage )
PPUBANK[ nPage ] = VROMPAGE( nPage );
InfoNES_SetupChr();
}
/* Set up wiring of the interrupt pin */
K6502_Set_Int_Wiring( 1, 1 );
}
/*-------------------------------------------------------------------*/
/* Mapper 0 Write Function */
/*-------------------------------------------------------------------*/
void Map0_Write( WORD wAddr, BYTE byData )
{
/*
* Dummy Write to Mapper
*
*/
}
/*-------------------------------------------------------------------*/
/* Mapper 0 Write to SRAM Function */
/*-------------------------------------------------------------------*/
void Map0_Sram( WORD wAddr, BYTE byData )
{
/*
* Dummy Write to Sram
*
*/
}
/*-------------------------------------------------------------------*/
/* Mapper 0 Write to APU Function */
/*-------------------------------------------------------------------*/
void Map0_Apu( WORD wAddr, BYTE byData )
{
/*
* Dummy Write to Apu
*
*/
}
/*-------------------------------------------------------------------*/
/* Mapper 0 Read from APU Function */
/*-------------------------------------------------------------------*/
BYTE Map0_ReadApu( WORD wAddr )
{
/*
* Dummy Read from Apu
*
*/
return ( wAddr >> 8 );
}
/*-------------------------------------------------------------------*/
/* Mapper 0 V-Sync Function */
/*-------------------------------------------------------------------*/
void Map0_VSync()
{
/*
* Dummy Callback at VSync
*
*/
}
/*-------------------------------------------------------------------*/
/* Mapper 0 H-Sync Function */
/*-------------------------------------------------------------------*/
void Map0_HSync()
{
/*
* Dummy Callback at HSync
*
*/
#if 0
// Frame IRQ
FrameStep += STEP_PER_SCANLINE;
if ( FrameStep > STEP_PER_FRAME && FrameIRQ_Enable )
{
FrameStep %= STEP_PER_FRAME;
IRQ_REQ;
APU_Reg[ 0x4015 ] |= 0x40;
}
#endif
}
/*-------------------------------------------------------------------*/
/* Mapper 0 PPU Function */
/*-------------------------------------------------------------------*/
void Map0_PPU( WORD wAddr )
{
/*
* Dummy Callback at PPU
*
*/
}
/*-------------------------------------------------------------------*/
/* Mapper 0 Rendering Screen Function */
/*-------------------------------------------------------------------*/
void Map0_RenderScreen( BYTE byMode )
{
/*
* Dummy Callback at Rendering Screen
*
*/
}
/*===================================================================*/
/* */
/* Mapper 1 */
/* */
/*===================================================================*/
BYTE Map1_Regs[ 4 ];
DWORD Map1_Cnt;
BYTE Map1_Latch;
WORD Map1_Last_Write_Addr;
enum Map1_Size_t
{
Map1_SMALL,
Map1_512K,
Map1_1024K
};
Map1_Size_t Map1_Size;
DWORD Map1_256K_base;
DWORD Map1_swap;
// these are the 4 ROM banks currently selected
DWORD Map1_bank1;
DWORD Map1_bank2;
DWORD Map1_bank3;
DWORD Map1_bank4;
DWORD Map1_HI1;
DWORD Map1_HI2;
/*-------------------------------------------------------------------*/
/* Initialize Mapper 1 */
/*-------------------------------------------------------------------*/
void Map1_Init()
{
DWORD size_in_K;
/* Initialize Mapper */
MapperInit = Map1_Init;
/* Write to Mapper */
MapperWrite = Map1_Write;
/* Write to SRAM */
MapperSram = Map0_Sram;
/* Write to APU */
MapperApu = Map0_Apu;
/* Read from APU */
MapperReadApu = Map0_ReadApu;
/* Callback at VSync */
MapperVSync = Map0_VSync;
/* Callback at HSync */
MapperHSync = Map0_HSync;
/* Callback at PPU */
MapperPPU = Map0_PPU;
/* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */
MapperRenderScreen = Map0_RenderScreen;
/* Set SRAM Banks */
SRAMBANK = SRAM;
/* Initialize State Registers */
Map1_Cnt = 0;
Map1_Latch = 0x00;
Map1_Regs[ 0 ] = 0x0c;
Map1_Regs[ 1 ] = 0x00;
Map1_Regs[ 2 ] = 0x00;
Map1_Regs[ 3 ] = 0x00;
size_in_K = ( NesHeader.byRomSize << 1 ) * 8;
if ( size_in_K == 1024 )
{
Map1_Size = Map1_1024K;
}
else if(size_in_K == 512)
{
Map1_Size = Map1_512K;
}
else
{
Map1_Size = Map1_SMALL;
}
Map1_256K_base = 0; // use first 256K
Map1_swap = 0;
if( Map1_Size == Map1_SMALL )
{
// set two high pages to last two banks
Map1_HI1 = ( NesHeader.byRomSize << 1 ) - 2;
Map1_HI2 = ( NesHeader.byRomSize << 1 ) - 1;
}
else
{
// set two high pages to last two banks of current 256K region
Map1_HI1 = ( 256 / 8 ) - 2;
Map1_HI2 = ( 256 / 8 ) - 1;
}
// set CPU bank pointers
Map1_bank1 = 0;
Map1_bank2 = 1;
Map1_bank3 = Map1_HI1;
Map1_bank4 = Map1_HI2;
/* Set ROM Banks */
Map1_set_ROM_banks();
/* Set up wiring of the interrupt pin */
K6502_Set_Int_Wiring( 1, 1 );
}
void Map1_set_ROM_banks()
{
ROMBANK0 = ROMPAGE( ( (Map1_256K_base << 5) + (Map1_bank1 & ((256/8)-1)) ) % ( NesHeader.byRomSize << 1 ) );
ROMBANK1 = ROMPAGE( ( (Map1_256K_base << 5) + (Map1_bank2 & ((256/8)-1)) ) % ( NesHeader.byRomSize << 1 ) );
ROMBANK2 = ROMPAGE( ( (Map1_256K_base << 5) + (Map1_bank3 & ((256/8)-1)) ) % ( NesHeader.byRomSize << 1 ) );
ROMBANK3 = ROMPAGE( ( (Map1_256K_base << 5) + (Map1_bank4 & ((256/8)-1)) ) % ( NesHeader.byRomSize << 1 ) );
}
/*-------------------------------------------------------------------*/
/* Mapper 1 Write Function */
/*-------------------------------------------------------------------*/
void Map1_Write( WORD wAddr, BYTE byData )
{
/*
* MMC1
*/
DWORD dwRegNum;
// if write is to a different reg, reset
if( ( wAddr & 0x6000 ) != ( Map1_Last_Write_Addr & 0x6000 ) )
{
Map1_Cnt = 0;
Map1_Latch = 0x00;
}
Map1_Last_Write_Addr = wAddr;
// if bit 7 set, reset and return
if ( byData & 0x80 )
{
Map1_Cnt = 0;
Map1_Latch = 0x00;
return;
}
if ( byData & 0x01 ) Map1_Latch |= ( 1 << Map1_Cnt );
Map1_Cnt++;
if( Map1_Cnt < 5 ) return;
dwRegNum = ( wAddr & 0x7FFF ) >> 13;
Map1_Regs[ dwRegNum ] = Map1_Latch;
Map1_Cnt = 0;
Map1_Latch = 0x00;
switch( dwRegNum )
{
case 0:
{
// set mirroring
if( Map1_Regs[0] & 0x02 )
{
if( Map1_Regs[0] & 0x01 )
{
InfoNES_Mirroring( 0 );
}
else
{
InfoNES_Mirroring( 1 );
}
}
else
{
// one-screen mirroring
if( Map1_Regs[0] & 0x01 )
{
InfoNES_Mirroring( 2 );
}
else
{
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