rc531.c

RC531

       prescale = 0x15;
       reload   = 0xFF;				    // T = (reload - counter) / fcnt
    }
    Write_RF531(RegTimerClock,prescale); 	// TAutoRestart=0,TPrescale=prescale
    Write_RF531(RegTimerReload,reload);		// TReloadVal = reload
    
    return 1;
}
char  PcdSingleResponseCmd(U8 cmd,volatile U8* send,volatile U8* rcv, volatile MfCmdInfo *info)
{     
   	long status  = MI_OK;
   	U8 lastBits;
   	U8 validErrorFlags = 0x1F; 
   	U8 rxMultiple = 0x00;

   	U8 irqEn     = 0x00;
   	U8 waitFor   = 0x00;
   	U8 timerCtl  = 0x02;
   	U8 waterLevelBackup;
   	Write_RF531(RegInterruptEn,0x7F); // disable all interrupts
   	Write_RF531(RegInterruptRq,0x7F); // reset interrupt requests
   	// please pay attention to the sequence of following commands
   	// at first empty the FIFO
   	// second wait for probably e2 programming in progress
   	// third cancel command
   	//
  	 // ATTENTION: the guard timer must not expire earlier than 10 ms
   	FlushFIFO();            // flush FIFO buffer
   	// wait until e2 programming is finished
   	while (((Read_RF531(RegSecondaryStatus) & 0x40) == 0));
   	Write_RF531(RegCommand,PCD_IDLE); // terminate probably running command
   	// Set water level to the default value (see. 'PcdBasicRegisterConfiguration()')   
   	waterLevelBackup = Read_RF531(RegFIFOLevel);
   	Write_RF531(RegFIFOLevel,0x20);
   	// save info structures to module pointers
   	MpIsrInfo = info;  
   	MpIsrOut  = send;
   	MpIsrIn   = rcv;
   	info->irqSource = 0x0; // reset interrupt flags
   	//READER_INT_ENABLE;
   	// depending on the command code, appropriate interrupts are enabled (irqEn)
   	// and the commit interrupt is choosen (waitFor).
   	switch(cmd)
   	{
      	case PCD_IDLE:                   // nothing else required
         	irqEn = 0x00;
         	waitFor = 0x00;
         	break;
      	case PCD_WRITEE2:                // LoAlert and TxIRq
         	timerCtl = 0x00;              // start and stop timer manually            
         	irqEn = 0x11;
         	waitFor = 0x10;
		 	validErrorFlags &= ~0x08;     // hb 20.06.2001 don't check CRC errors         
         	break;
      	case PCD_READE2:                 // HiAlert, LoAlert and IdleIRq
         	timerCtl = 0x00;              // start and stop timer manually            
         	irqEn = 0x07;
         	waitFor = 0x04;
		 	validErrorFlags &= ~0x08;     // wu 15.05.2001 don't check CRC errors
         	break;
      	case PCD_LOADKEYE2:              // IdleIRq and LoAlert
         	timerCtl = 0x00;              // start and stop timer manually            
		 	validErrorFlags &= ~0x08;     // hb 20.06.2001 don't check CRC errors               
         	irqEn = 0x05;
         	waitFor = 0x04;
         	break;
      	case PCD_LOADCONFIG:             // IdleIRq and LoAlert
         	timerCtl = 0x00;              // start and stop timer manually            
         	irqEn = 0x05;
         	waitFor = 0x04;
         	break;
      	case PCD_AUTHENT1:               // IdleIRq and LoAlert
         	irqEn = 0x05;
         	waitFor = 0x04;
         	break;
      	case PCD_CALCCRC:                // LoAlert and TxIRq
         	timerCtl = 0x00;              // start and stop timer manually            
         	irqEn = 0x11;
         	waitFor = 0x10;
         	break;
      	case PCD_AUTHENT2:               // IdleIRq
         	irqEn = 0x04;
         	waitFor = 0x04;
         	break;
     	case PCD_RECEIVE:                // HiAlert and IdleIRq
         	info->nBitsReceived = -(Read_RF531(RegBitFraming) >> 4);      
         	timerCtl = 0x04;              // start timer manually and stop
                                       // with first bit received
         	irqEn = 0x06;
         	waitFor = 0x04;
         	break;
      	case PCD_LOADKEY:                // IdleIRq
         	timerCtl = 0x00;              // start and stop timer manually            
         	irqEn = 0x05;
         	waitFor = 0x04;
        	break;
      	case PCD_TRANSMIT:               // LoAlert and IdleIRq
         	timerCtl = 0x00;              // start and stop timer manually            
         	irqEn = 0x05;
         	waitFor = 0x04;
         	break;
      	case PCD_TRANSCEIVE:             // TxIrq, RxIrq, IdleIRq and LoAlert
         	info->nBitsReceived = -(Read_RF531(RegBitFraming) >> 4);
         	irqEn = 0x3D;
         	waitFor = 0x04;
         	break;
      	default:
         	status = MI_UNKNOWN_COMMAND;
   	}        
   	if (status == MI_OK)
   	{
      	rxMultiple = Read_RF531(RegDecoderControl) & 0x40;
      	if (!rxMultiple)
         	SetBitMask(RegDecoderControl,0x40);    
      	// Initialize uC Timer for global Timeout management
      	irqEn |= 0x20;                        // always enable timout irq
      	waitFor |= 0x20;                      // always wait for timeout 
      	Write_RF531(RegInterruptEn,irqEn | 0x80);  //necessary interrupts are enabled // count up from 1     
      	Write_RF531(RegTimerControl,timerCtl);
      	if (~timerCtl & 0x02){ // if no start condition could be detected, then
                              // start timer manually
         	SetBitMask(RegControl,0x02);
      	}
      	Write_RF531(RegCommand,cmd);               //start command   
      	// wait for commmand completion
      	// a command is completed, if the corresponding interrupt occurs
      	// or a timeout is signaled  
      	while (!(MpIsrInfo->irqSource & waitFor)); // wait for cmd completion or timeout
      	SetBitMask(RegControl,0x04);         // stop timer now
      	Write_RF531(RegInterruptEn,0x7F);          // disable all interrupts
      	Write_RF531(RegInterruptRq,0x7F);          // clear all interrupt requests
      	Write_RF531(RegCommand,PCD_IDLE);          // reset command register
      	status = MpIsrInfo->status;          // set status
      	if (MpIsrInfo->irqSource & 0x20) // if timeout expired - look at old error state
        	MpIsrInfo->errFlags |= MpIsrInfo->saveErrorState;
      	MpIsrInfo->errFlags &=  validErrorFlags;
      	if (MpIsrInfo->errFlags){ // error occured
         	if (MpIsrInfo->errFlags & 0x01){   // collision detected
            	info->collPos = Read_RF531(RegCollPos); // read collision position
            	status = MI_COLLERR;
         	}else{
            	if (MpIsrInfo->errFlags & 0x02){   // parity error
               		status = MI_PARITYERR;
            	}
         	}
         	if (MpIsrInfo->errFlags & 0x04){   // framing error
            	status = MI_FRAMINGERR;
         	}else if (MpIsrInfo->errFlags & 0x10){   // FIFO overflow
            	FlushFIFO();
            	status = MI_OVFLERR;
         	}else if (MpIsrInfo->errFlags & 0x08){ // CRC error
            	status = MI_CRCERR;
         	}else if (status == MI_OK)
            	status = MI_NY_IMPLEMENTED;
         		// key error occures always, because of 
         		// missing crypto 1 keys loaded
      	}
      		// if the last command was TRANSCEIVE, the number of 
      		// received bits must be calculated - even if an error occured
      	if (cmd == PCD_TRANSCEIVE || cmd == PCD_RECEIVE){
         	// number of bits in the last byte
         	lastBits = Read_RF531(RegSecondaryStatus) & 0x07;
         	if (lastBits)
            	info->nBitsReceived += (info->nBytesReceived-1) * 8 + lastBits;
         	else
            	info->nBitsReceived += info->nBytesReceived * 8;
      	}     
      	if (!rxMultiple)
         	ClearBitMask(RegDecoderControl,0x40);
   		}	
  	// READER_INT_DISABLE;
   	MpIsrInfo = 0;         // reset interface variables for ISR
   	MpIsrOut  = 0;
   	MpIsrIn   = 0; 
   	// restore the previous value for the FIFO water level
   	Write_RF531(RegFIFOLevel, waterLevelBackup);
   	return status;
} 
  
void memcpy(void *dest, void *src, U32 len)							//拷贝
{
	U32 i;
	U8 *p1, *p2;
	p1=(U8*)src;  p2=(U8*)dest;
	for(i=0; i<len; i++){
		*p2=*p1;  p1++;  p2++;
	}
}


U8 Mf500PiccCommonRequest(U8 req_code, 
                            U8 *atq)
{
   	long status;

    //************* initialize ******************************
   	if ((status = Mf500PcdSetDefaultAttrib()) == 1)
   	{   
      PcdSetTmo(60);      
      Write_RF531(RegChannelRedundancy,0x03); // RxCRC and TxCRC disable, parity enable
      ClearBitMask(RegControl,0x08);      // disable crypto 1 unit   
      Write_RF531(RegBitFraming,0x07);        // set TxLastBits to 7      
      ResetInfo(MInfo);   
      MSndBuffer[0] = req_code;
      MInfo.nBytesToSend   = 1;   
      MInfo.DisableDF = 1;
      status = PcdSingleResponseCmd(PCD_TRANSCEIVE,
                         MSndBuffer,
                         MRcvBuffer,
                         &MInfo);
      if ((status == MI_OK) && (MInfo.nBitsReceived != 16)) // 2 bytes expected
      {
         status = MI_BITCOUNTERR;
      } 
      if ((status == MI_COLLERR) && (MInfo.nBitsReceived == 16)) //
         status = MI_OK; // all received tag-types are combined to the 16 bit
         
      // in any case, copy received data to output - for debugging reasons
      if (MInfo.nBytesReceived >= 2)
      {
         memcpy(atq,(void *)MRcvBuffer,2);      
      }
      else
      {
         if (MInfo.nBytesReceived == 1)
            atq[0] = MRcvBuffer[0];
         else
            atq[0] = 0x00;
         atq[1] = 0x00;
      }
   }
   return status; 
}