📄 pxa255.h
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#ifndef PXA255_H
#define PXA255_H
#define U8 unsigned char
#define U16 unsigned short
#define U32 unsigned int
#define REG8 volatile unsigned char
#define REG16 volatile unsigned short
#define REG32 volatile unsigned int
#define VPchar *(REG8 *)
#define VPshort *(REG16 *)
#define VPint *(REG32 *)
#define Pchar (REG8 *)
#define Pshort (REG16 *)
#define Pint (REG32 *)
#define CORE_CLK_100M 0x121
#define CORE_CLK_200M 0x141
#define CORE_CLK_400M 0x161
// GPIO
#define BASE_GPIO 0x40E00000
#define GPLR0 (VPint(BASE_GPIO)) // GPIO[00..31] Pin Level Register
#define GPLR1 (VPint(BASE_GPIO+0x04)) // GPIO[32..63] Pin Level Register
#define GPLR2 (VPint(BASE_GPIO+0x08)) // GPIO[64..84] Pin Level Register
#define GPDR0 (VPint(BASE_GPIO+0x0C)) // GPIO[00..31] Pin Direction Register(1=output)
#define GPDR1 (VPint(BASE_GPIO+0x10)) // GPIO[32..63] Pin Direction Register(1=output)
#define GPDR2 (VPint(BASE_GPIO+0x14)) // GPIO[64..84] Pin Direction Register(1=output)
#define GPSR0 (VPint(BASE_GPIO+0x18)) // GPIO[00..31] Output Set Register
#define GPSR1 (VPint(BASE_GPIO+0x1C)) // GPIO[32..63] Output Set Register
#define GPSR2 (VPint(BASE_GPIO+0x20)) // GPIO[64..84] Output Set Register
#define GPCR0 (VPint(BASE_GPIO+0x24)) // GPIO[00..31] Output Clear Register
#define GPCR1 (VPint(BASE_GPIO+0x28)) // GPIO[32..63] Output Clear Register
#define GPCR2 (VPint(BASE_GPIO+0x2C)) // GPIO[64..84] Output Clear Register
#define GRER0 (VPint(BASE_GPIO+0x30)) // GPIO[00..31] Rising Edge Detect Enable Register
#define GRER1 (VPint(BASE_GPIO+0x34)) // GPIO[32..63] Rising Edge Detect Enable Register
#define GRER2 (VPint(BASE_GPIO+0x38)) // GPIO[64..84] Rising Edge Detect Enable Register
#define GFER0 (VPint(BASE_GPIO+0x3C)) // GPIO[00..31] Falling Edge Detect Enable Register
#define GFER1 (VPint(BASE_GPIO+0x40)) // GPIO[32..63] Falling Edge Detect Enable Register
#define GFER2 (VPint(BASE_GPIO+0x44)) // GPIO[64..84] Falling Edge Detect Enable Register
#define GEDR0 (VPint(BASE_GPIO+0x48)) // GPIO[00..31] Edge Detect Status Register
#define GEDR1 (VPint(BASE_GPIO+0x4C)) // GPIO[32..63] Edge Detect Status Register
#define GEDR2 (VPint(BASE_GPIO+0x50)) // GPIO[64..84] Edge Detect Status Register
#define GAFR0_L (VPint(BASE_GPIO+0x54)) // GPIO[00..15] Alternate Function(00=normal GPIO)
#define GAFR0_U (VPint(BASE_GPIO+0x58)) // GPIO[16..31] Alternate Function(00=normal GPIO)
#define GAFR1_L (VPint(BASE_GPIO+0x5C)) // GPIO[32..47] Alternate Function(00=normal GPIO)
#define GAFR1_U (VPint(BASE_GPIO+0x60)) // GPIO[48..63] Alternate Function(00=normal GPIO)
#define GAFR2_L (VPint(BASE_GPIO+0x64)) // GPIO[64..79] Alternate Function(00=normal GPIO)
#define GAFR2_U (VPint(BASE_GPIO+0x68)) // GPIO[80..84] Alternate Function(00=normal GPIO)
// Clock
#define BASE_CLOCK 0x41300000
#define CCCR (VPint(BASE_CLOCK))
#define CKEN (VPint(BASE_CLOCK+0x04))
#define OSCC (VPint(BASE_CLOCK+0x08))
// Memory
#define BASE_MEM 0x48000000
#define MDCNFG (VPint(BASE_MEM)) // SDRAM Configuration Register
#define MDREFR (VPint(BASE_MEM+0x04)) // SDRAM Refresh Control Register
#define MDMRS (VPint(BASE_MEM+0x40)) // MRS value to be written to SDRAM
#define MSC0 (VPint(BASE_MEM+0x08)) // Asynchronous Static Memory Control Register
#define MSC1 (VPint(BASE_MEM+0x0C)) // Asynchronous Static Memory Control Register
#define MSC2 (VPint(BASE_MEM+0x10)) // Asynchronous Static Memory Control Register
// FF UART
#define BASE_FFUART 0x40100000
#define FFRBR (VPint(BASE_FFUART)) // Receive Buffer Register(read only)
#define FFTHR (VPint(BASE_FFUART)) // Transmit Holding Register(write only)
#define FFIER (VPint(BASE_FFUART+0x04)) // Interrupt Enable Register
#define FFIIR (VPint(BASE_FFUART+0x08)) // Interrupt Identification Register(read only)
#define FFFCR (VPint(BASE_FFUART+0x08)) // FIFO Control Register(write only)
#define FFLCR (VPint(BASE_FFUART+0x0C)) // Line Control Register(DLAB=bit7)
#define FFMCR (VPint(BASE_FFUART+0x10)) // Modem Control Register
#define FFLSR (VPint(BASE_FFUART+0x14)) // Line Status Register(read only)
#define FFMSR (VPint(BASE_FFUART+0x18)) // Modem Status Register(read only)
#define FFSPR (VPint(BASE_FFUART+0x1C)) // Scratchpad Register
#define FFISR (VPint(BASE_FFUART+0x20)) // Infrared Selection Register
#define FFDLL (VPint(BASE_FFUART)) // Divisor Latch Low register(DLAB=1)
#define FFDLH (VPint(BASE_FFUART+0x04)) // Divisor Latch High register(DLAB=1)
// BT UART
#define BASE_BTUART 0x40200000
#define BTRBR (VPint(BASE_BTUART)) // Receive Buffer Register(read only)
#define BTTHR (VPint(BASE_BTUART)) // Transmit Holding Register(write only)
#define BTIER (VPint(BASE_BTUART+0x04)) // Interrupt Enable Register
#define BTIIR (VPint(BASE_BTUART+0x08)) // Interrupt Identification Register(read only)
#define BTFCR (VPint(BASE_BTUART+0x08)) // FIFO Control Register(write only)
#define BTLCR (VPint(BASE_BTUART+0x0C)) // Line Control Register(DLAB=bit7)
#define BTMCR (VPint(BASE_BTUART+0x10)) // Modem Control Register
#define BTLSR (VPint(BASE_BTUART+0x14)) // Line Status Register(read only)
#define BTMSR (VPint(BASE_BTUART+0x18)) // Modem Status Register(read only)
#define BTSPR (VPint(BASE_BTUART+0x1C)) // Scratchpad Register
#define BTISR (VPint(BASE_BTUART+0x20)) // Infrared Selection Register
#define BTDLL (VPint(BASE_BTUART)) // Divisor Latch Low register(DLAB=1)
#define BTDLH (VPint(BASE_BTUART+0x04)) // Divisor Latch High register(DLAB=1)
// ST UART
#define BASE_STUART 0x40700000
#define STRBR (VPint(BASE_STUART)) // Receive Buffer Register(read only)
#define STTHR (VPint(BASE_STUART)) // Transmit Holding Register(write only)
#define STIER (VPint(BASE_STUART+0x04)) // Interrupt Enable Register
#define STIIR (VPint(BASE_STUART+0x08)) // Interrupt Identification Register(read only)
#define STFCR (VPint(BASE_STUART+0x08)) // FIFO Control Register(write only)
#define STLCR (VPint(BASE_STUART+0x0C)) // Line Control Register(DLAB=bit7)
#define STMCR (VPint(BASE_STUART+0x10)) // Modem Control Register
#define STLSR (VPint(BASE_STUART+0x14)) // Line Status Register(read only)
#define STMSR (VPint(BASE_STUART+0x18)) // Modem Status Register(read only)
#define STSPR (VPint(BASE_STUART+0x1C)) // Scratchpad Register
#define STISR (VPint(BASE_STUART+0x20)) // Infrared Selection Register
#define STDLL (VPint(BASE_STUART)) // Divisor Latch Low register(DLAB=1)
#define STDLH (VPint(BASE_STUART+0x04)) // Divisor Latch High register(DLAB=1)
// HW UART
#define BASE_HWUART 0x41600000
#define HWRBR (VPint(BASE_HWUART)) // Receive Buffer Register(read only)
#define HWTHR (VPint(BASE_HWUART)) // Transmit Holding Register(write only)
#define HWIER (VPint(BASE_HWUART+0x04)) // Interrupt Enable Register
#define HWIIR (VPint(BASE_HWUART+0x08)) // Interrupt Identification Register(read only)
#define HWFCR (VPint(BASE_HWUART+0x08)) // FIFO Control Register(write only)
#define HWLCR (VPint(BASE_HWUART+0x0C)) // Line Control Register(DLAB=bit7)
#define HWMCR (VPint(BASE_HWUART+0x10)) // Modem Control Register
#define HWLSR (VPint(BASE_HWUART+0x14)) // Line Status Register(read only)
#define HWMSR (VPint(BASE_HWUART+0x18)) // Modem Status Register(read only)
#define HWSPR (VPint(BASE_HWUART+0x1C)) // Scratchpad Register
#define HWISR (VPint(BASE_HWUART+0x20)) // Infrared Selection Register
#define HWDLL (VPint(BASE_HWUART)) // Divisor Latch Low register(DLAB=1)
#define HWDLH (VPint(BASE_HWUART+0x04)) // Divisor Latch High register(DLAB=1)
// OS Timer
#define OS_TIMER 0x40A00000
#define OSCR (VPint(OS_TIMER+0x10)) // OS Timer Counter Register(1us+3.6864)
#define OSMR3 (VPint(OS_TIMER+0x0C))
#define OWER (VPint(OS_TIMER+0x18))
// RTC Timer
#define RTC_TIMER 0x40900000
#define RCNR (VPint(RTC_TIMER)) // RTC Counter Register(1s+1)
// IIC Bus
#define BASE_IIC 0x40301600
#define IBMR (VPint(BASE_IIC+0x80)) // IIC Bus Monitor Register
#define IDBR (VPint(BASE_IIC+0x88)) // IIC Data Buffer Register
#define ICR (VPint(BASE_IIC+0x90)) // IIC Control Register
#define ISR (VPint(BASE_IIC+0x98)) // IIC Status Register
#define ISAR (VPint(BASE_IIC+0xA0)) // IIC Slave Address Register
#define I2CCR (VPint(BASE_IIC+0xA8)) // IIC Clock Count Register
// ICR bit define
#define ICR_FM (1<<15) // 1=Fast Mode(400Kbit/s)
#define ICR_UR (1<<14) // 1=Unit Reset
#define ICR_SADIE (1<<13) // 1=Slave Address Detected Interrupt Enable
#define ICR_ALDIE (1<<12) // 1=Arbitration Loss Detected Interrupt Enable
#define ICR_SSDIE (1<<11) // 1=Slave STOP Detected Interrupt Enable
#define ICR_BEIE (1<<10) // 1=Bus Error Interrupt Enable
#define ICR_IRFIE (1<<9) // 1=IDBR Receive Full Interrupt Enable
#define ICR_ITEIE (1<<8) // 1=IDBR Transmit Empty Interrupt Enable
#define ICR_GCD (1<<7) // 1=General Call Disable
#define ICR_IUE (1<<6) // 1=IIC Unit Enable
#define ICR_SCLE (1<<5) // 1=SCL Enable
#define ICR_MA (1<<4) // Master Abort
#define ICR_TB (1<<3) // Transfer Byte
#define ICR_ACKNAK (1<<2) // 0=ACK control
#define ICR_STOP (1<<1) // 1=Send a STOP
#define ICR_START (1) // 1=Send a START
// ISR bit define
#define ISR_BED (1<<10) // Bus Error Detected
#define ISR_SAD (1<<9) // Slave Address Detected
#define ISR_GCAD (1<<8) // General Call Address Detected
#define ISR_IRF (1<<7) // IDBR Receive Full
#define ISR_ITE (1<<6) // IDBR Transmit Empty
#define ISR_ALD (1<<5) // Arbitration Loss Detected
#define ISR_SSD (1<<4) // Slave STOP Detected
#define ISR_IBB (1<<3) // IIC Bus Busy
#define ISR_UB (1<<2) // Unit Busy
#define ACKNAK (1<<1) // ACK/NAK Status
#define ISR_RWM (1) // Read/Write Mode
// Power Manager
#define BASE_POWER 0x40F00000
#define PSSR (VPint(BASE_POWER+0x04)) // Must write a 0x20 to enable GPIO input
// DM9000E use nCS3
#define BASE_DM9000 0x0C000000
#define DM9000_ADDR (VPint(BASE_DM9000))
#define DM9000_DATA (VPint(BASE_DM9000+0x04))
// SL811 use nCS2
#define BASE_RC531 0x08000000
#define gFlash32 (Pint(0)) // MMU Disable
//#define gFlash16 (Pshort(0xFF800000)) / // MMU Enable
#define gFlash16 (Pshort(0xFF800000)) // MMU Enable
#define g0Flash16 (Pshort(0)) // MMU Disable
#define IP_HEAD 14
#define UDP_HEAD 34
#define TempFlash16 ((U16 *)0xFF900000)
#define Template8 ((U8 *)0xA0600000) // Template buffer
#define Template16 ((U16 *)0xA0600000)
//#define Template32 ((U32 *)0xA0600000)
#define gImgBuf ((U8 *)0xA0400000) // start at 5M
//#define Finger_Buf ((U8 *)0xA0400000) // start at 4M
#define G_on GPSR0=0x20;
#define G_off GPCR0=0x20;
#define R_on GPSR0=0x40;
#define R_off GPCR0=0x40;
#define BT_RetH GPSR0=0x800000;
#define BT_RetL GPCR0=0x800000;
//rf531
void Delay_us(U32 us) ;
#define ALE_L GPCR2=0x2000;
#define ALE_H GPSR2=0x2000;
#define RF531_RESET GPSR2=0x800;
#define RF531_CLEAR_RESET GPCR2=0x800;
#define Write_RE(addr,dat) (VPint(BASE_RC531+addr*4))=dat
#define Read_RE(addr) (VPint(BASE_RC531+addr*4))
#endif
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