📄 c8051f040.lst
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260 sbit EWARN = CAN0STA ^ 6; /* Warning Status */
261 sbit EPASS = CAN0STA ^ 5; /* Error Passive */
262 sbit RXOK = CAN0STA ^ 4; /* Received Message Successfully */
263 sbit TXOK = CAN0STA ^ 3; /* Transmit a Message Successfully */
264 sbit LEC2 = CAN0STA ^ 2; /* Last error code bit 2 */
265 sbit LEC1 = CAN0STA ^ 1; /* Last error code bit 1 */
266 sbit LEC0 = CAN0STA ^ 0; /* Last error code bit */
267
268 /* TMR2CN 0xC8 */
269 sbit TF2 = TMR2CN ^ 7; /* TIMER 2 OVERFLOW FLAG */
270 sbit EXF2 = TMR2CN ^ 6; /* TIMER 2 EXTERNAL FLAG */
271 sbit EXEN2 = TMR2CN ^ 3; /* TIMER 2 EXTERNAL ENABLE FLAG */
272 sbit TR2 = TMR2CN ^ 2; /* TIMER 2 ON/OFF CONTROL */
273 sbit CT2 = TMR2CN ^ 1; /* TIMER 2 COUNTER SELECT */
274 sbit CPRL2 = TMR2CN ^ 0; /* TIMER 2 CAPTURE SELECT */
275
276 /* TMR3CN 0xC8 */
277 sbit TF3 = TMR3CN ^ 7; /* TIMER 3 OVERFLOW FLAG */
278 sbit EXF3 = TMR3CN ^ 6; /* TIMER 3 EXTERNAL FLAG */
279 sbit EXEN3 = TMR3CN ^ 3; /* TIMER 3 EXTERNAL ENABLE FLAG */
280 sbit TR3 = TMR3CN ^ 2; /* TIMER 3 ON/OFF CONTROL */
281 sbit CT3 = TMR3CN ^ 1; /* TIMER 3 COUNTER SELECT */
282 sbit CPRL3 = TMR3CN ^ 0; /* TIMER 3 CAPTURE SELECT */
283
284 /* TMR4CN 0xC8 */
285 sbit TF4 = TMR4CN ^ 7; /* TIMER 4 OVERFLOW FLAG */
286 sbit EXF4 = TMR4CN ^ 6; /* TIMER 4 EXTERNAL FLAG */
287 sbit EXEN4 = TMR4CN ^ 3; /* TIMER 4 EXTERNAL ENABLE FLAG */
288 sbit TR4 = TMR4CN ^ 2; /* TIMER 4 ON/OFF CONTROL */
289 sbit CT4 = TMR4CN ^ 1; /* TIMER 4 COUNTER SELECT */
290 sbit CPRL4 = TMR4CN ^ 0; /* TIMER 4 CAPTURE SELECT */
291
292 /* PSW 0xD0 */
293 sbit CY = PSW ^ 7; /* CARRY FLAG */
294 sbit AC = PSW ^ 6; /* AUXILIARY CARRY FLAG */
295 sbit F0 = PSW ^ 5; /* USER FLAG 0 */
296 sbit RS1 = PSW ^ 4; /* REGISTER BANK SELECT 1 */
297 sbit RS0 = PSW ^ 3; /* REGISTER BANK SELECT 0 */
298 sbit OV = PSW ^ 2; /* OVERFLOW FLAG */
299 sbit F1 = PSW ^ 1; /* USER FLAG 1 */
300 sbit P = PSW ^ 0; /* ACCUMULATOR PARITY FLAG */
301
302 /* PCA0CN 0xD8 */
303 sbit CF = PCA0CN ^ 7; /* PCA 0 COUNTER OVERFLOW FLAG */
C51 COMPILER V6.23a C8051F040 12/14/2004 13:09:06 PAGE 6
304 sbit CR = PCA0CN ^ 6; /* PCA 0 COUNTER RUN CONTROL BIT */
305 sbit CCF5 = PCA0CN ^ 5; /* PCA 0 MODULE 5 INTERRUPT FLAG */
306 sbit CCF4 = PCA0CN ^ 4; /* PCA 0 MODULE 4 INTERRUPT FLAG */
307 sbit CCF3 = PCA0CN ^ 3; /* PCA 0 MODULE 3 INTERRUPT FLAG */
308 sbit CCF2 = PCA0CN ^ 2; /* PCA 0 MODULE 2 INTERRUPT FLAG */
309 sbit CCF1 = PCA0CN ^ 1; /* PCA 0 MODULE 1 INTERRUPT FLAG */
310 sbit CCF0 = PCA0CN ^ 0; /* PCA 0 MODULE 0 INTERRUPT FLAG */
311
312
313 /* ADC0CN 0xE8 */
314 sbit AD0EN = ADC0CN ^ 7; /* ADC 0 ENABLE */
315 sbit AD0TM = ADC0CN ^ 6; /* ADC 0 TRACK MODE */
316 sbit AD0INT = ADC0CN ^ 5; /* ADC 0 EOC INTERRUPT FLAG */
317 sbit AD0BUSY = ADC0CN ^ 4; /* ADC 0 BUSY FLAG */
318 sbit AD0CM1 = ADC0CN ^ 3; /* ADC 0 CONVERT START MODE BIT 1 */
319 sbit AD0CM0 = ADC0CN ^ 2; /* ADC 0 CONVERT START MODE BIT 0 */
320 sbit AD0WINT = ADC0CN ^ 1; /* ADC 0 WINDOW INTERRUPT FLAG */
321
322
323 /* ADC2CN 0xE8 */
324 sbit AD2EN = ADC2CN ^ 7; /* ADC 2 ENABLE */
325 sbit AD2TM = ADC2CN ^ 6; /* ADC 2 TRACK MODE */
326 sbit AD2INT = ADC2CN ^ 5; /* ADC 2 EOC INTERRUPT FLAG */
327 sbit AD2BUSY = ADC2CN ^ 4; /* ADC 2 BUSY FLAG */
328 sbit AD2WINT = ADC2CN ^ 3; /* ADC 2 WINDOW INTERRUPT FLAG */
329 sbit AD2CM2 = ADC2CN ^ 2; /* ADC 2 CONVERT START MODE BIT 2 */
330 sbit AD2CM1 = ADC2CN ^ 1; /* ADC 2 CONVERT START MODE BIT 1 */
331 sbit AD2CM0 = ADC2CN ^ 0; /* ADC 2 CONVERT START MODE BIT 0 */
332
333 /* SPI0CN 0xF8 */
334 sbit SPIF = SPI0CN ^ 7; /* SPI 0 INTERRUPT FLAG */
335 sbit WCOL = SPI0CN ^ 6; /* SPI 0 WRITE COLLISION FLAG */
336 sbit MODF = SPI0CN ^ 5; /* SPI 0 MODE FAULT FLAG */
337 sbit RXOVRN = SPI0CN ^ 4; /* SPI 0 RX OVERRUN FLAG */
338 sbit NSSMD1 = SPI0CN ^ 3; /* SPI 0 SLAVE SELECT MODE BIT 1 */
339 sbit NSSMD0 = SPI0CN ^ 2; /* SPI 0 SLAVE SELECT MODE BIT 0 */
340 sbit TXBMT = SPI0CN ^ 1; /* SPI 0 TX BUFFER EMPTY */
341 sbit SPIEN = SPI0CN ^ 0; /* SPI 0 SPI ENABLE */
342
343 /* CAN0CN 0xF8 */
344 sbit CANINIT = CAN0CN ^ 0; /* CAN Initialization bit */
345 sbit CANIE = CAN0CN ^ 1; /* CAN Module Interrupt Enable Bit */
346 sbit CANSIE = CAN0CN ^ 2; /* CAN Status change Interrupt Enable Bit */
347 sbit CANEIE = CAN0CN ^ 3; /* CAN Module Error Interrupt Enable Bit */
348 sbit CANIF = CAN0CN ^ 4; /* CAN Module Interrupt Flag */
349 sbit CANDAR = CAN0CN ^ 5; /* CAN Disable Automatic Retransmission bit */
350 sbit CANCCE = CAN0CN ^ 6; /* CAN Configuration Change Enable bit */
351 sbit CANTEST = CAN0CN ^ 7; /* CAN Test Mode Enable bit */
352
353
354
355 /* SFR PAGE DEFINITIONS */
356 #define CONFIG_PAGE 0x0F /* SYSTEM AND PORT CONFIGURATION PAGE */
357 #define LEGACY_PAGE 0x00 /* LEGACY SFR PAGE */
358 #define TIMER01_PAGE 0x00 /* TIMER 0 AND TIMER 1 */
359 #define CPT0_PAGE 0x01 /* COMPARATOR 0 */
360 #define CPT1_PAGE 0x02 /* COMPARATOR 1 */
361 #define CPT2_PAGE 0x03 /* COMPARATOR 2 */
362 #define UART0_PAGE 0x00 /* UART 0 */
363 #define UART1_PAGE 0x01 /* UART 1 */
364 #define SPI0_PAGE 0x00 /* SPI 0 */
365 #define EMI0_PAGE 0x00 /* EXTERNAL MEMORY INTERFACE */
C51 COMPILER V6.23a C8051F040 12/14/2004 13:09:06 PAGE 7
366 #define ADC0_PAGE 0x00 /* ADC 0 */
367 #define ADC2_PAGE 0x02 /* ADC 2 */
368 #define SMB0_PAGE 0x00 /* SMBUS 0 */
369 #define TMR2_PAGE 0x00 /* TIMER 2 */
370 #define TMR3_PAGE 0x01 /* TIMER 3 */
371 #define TMR4_PAGE 0x02 /* TIMER 4 */
372 #define DAC0_PAGE 0x00 /* DAC 0 */
373 #define DAC1_PAGE 0x01 /* DAC 1 */
374 #define PCA0_PAGE 0x00 /* PCA 0 */
375 #define CAN0_PAGE 0x01 /* CAN 0 */
376
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = ---- ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = ---- ----
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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