📄 c8051f040.lst
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126 sfr PCA0MD = 0xD9; /* PCA 0 COUNTER MODE */
127 sfr CAN0DATH = 0xD9; /* CAN 0 DATA - HIGH BYTE */
128 sfr PCA0CPM0 = 0xDA; /* PCA 0 MODULE 0 CONTROL */
129 sfr CAN0ADR = 0xDA; /* CAN 0 ADDRESS */
130 sfr PCA0CPM1 = 0xDB; /* PCA 0 MODULE 1 CONTROL */
131 sfr CAN0TST = 0xDB; /* CAN 0 TEST */
132 sfr PCA0CPM2 = 0xDC; /* PCA 0 MODULE 2 CONTROL */
133 sfr PCA0CPM3 = 0xDD; /* PCA 0 MODULE 3 CONTROL */
134 sfr PCA0CPM4 = 0xDE; /* PCA 0 MODULE 4 CONTROL */
135 sfr PCA0CPM5 = 0xDF; /* PCA 0 MODULE 5 CONTROL */
136 sfr ACC = 0xE0; /* ACCUMULATOR */
137 sfr PCA0CPL5 = 0xE1; /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */
138 sfr XBR0 = 0xE1; /* CROSSBAR CONFIGURATION REGISTER 0 */
139 sfr PCA0CPH5 = 0xE2; /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */
140 sfr XBR1 = 0xE2; /* CROSSBAR CONFIGURATION REGISTER 1 */
141 sfr XBR2 = 0xE3; /* CROSSBAR CONFIGURATION REGISTER 2 */
142 sfr XBR3 = 0xE4; /* CROSSBAR CONFIGURATION REGISTER 3 */
143 sfr EIE1 = 0xE6; /* EXTERNAL INTERRUPT ENABLE 1 */
144 sfr EIE2 = 0xE7; /* EXTERNAL INTERRUPT ENABLE 2 */
145 sfr ADC0CN = 0xE8; /* ADC 0 CONTROL */
146 sfr ADC2CN = 0xE8; /* ADC 2 CONTROL */
147 sfr P6 = 0xE8; /* PORT 6 */
148 sfr PCA0CPL2 = 0xE9; /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */
149 sfr PCA0CPH2 = 0xEA; /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */
150 sfr PCA0CPL3 = 0xEB; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */
151 sfr PCA0CPH3 = 0xEC; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */
152 sfr PCA0CPL4 = 0xED; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */
153 sfr PCA0CPH4 = 0xEE; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */
154 sfr RSTSRC = 0xEF; /* RESET SOURCE */
155 sfr B = 0xF0; /* B REGISTER */
156 sfr EIP1 = 0xF6; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
157 sfr EIP2 = 0xF7; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
158 sfr SPI0CN = 0xF8; /* SPI 0 CONTROL */
159 sfr CAN0CN = 0xF8; /* CAN 0 CONTROL */
160 sfr P7 = 0xF8; /* PORT 7 */
161 sfr PCA0L = 0xF9; /* PCA 0 TIMER - LOW BYTE */
162 sfr PCA0H = 0xFA; /* PCA 0 TIMER - HIGH BYTE */
163 sfr PCA0CPL0 = 0xFB; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */
164 sfr PCA0CPH0 = 0xFC; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */
165 sfr PCA0CPL1 = 0xFD; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */
166 sfr PCA0CPH1 = 0xFE; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */
167 sfr WDTCN = 0xFF; /* WATCHDOG TIMER CONTROL */
168
169
170 /* BIT Registers */
171
172 /* TCON 0x88 */
173 sbit TF1 = TCON ^ 7; /* TIMER 1 OVERFLOW FLAG */
174 sbit TR1 = TCON ^ 6; /* TIMER 1 ON/OFF CONTROL */
175 sbit TF0 = TCON ^ 5; /* TIMER 0 OVERFLOW FLAG */
176 sbit TR0 = TCON ^ 4; /* TIMER 0 ON/OFF CONTROL */
177 sbit IE1 = TCON ^ 3; /* EXT. INTERRUPT 1 EDGE FLAG */
178 sbit IT1 = TCON ^ 2; /* EXT. INTERRUPT 1 TYPE */
179 sbit IE0 = TCON ^ 1; /* EXT. INTERRUPT 0 EDGE FLAG */
C51 COMPILER V6.23a C8051F040 12/14/2004 13:09:06 PAGE 4
180 sbit IT0 = TCON ^ 0; /* EXT. INTERRUPT 0 TYPE */
181
182 /* CPT0CN 0x88 */
183 sbit CP0EN = CPT0CN ^ 7; /* COMPARATOR 0 ENABLE */
184 sbit CP0OUT = CPT0CN ^ 6; /* COMPARATOR 0 OUTPUT */
185 sbit CP0RIF = CPT0CN ^ 5; /* COMPARATOR 0 RISING EDGE INTERRUPT */
186 sbit CP0FIF = CPT0CN ^ 4; /* COMPARATOR 0 FALLING EDGE INTERRUPT */
187 sbit CP0HYP1 = CPT0CN ^ 3; /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */
188 sbit CP0HYP0 = CPT0CN ^ 2; /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */
189 sbit CP0HYN1 = CPT0CN ^ 1; /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */
190 sbit CP0HYN0 = CPT0CN ^ 0; /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */
191
192 /* CPT1CN 0x88 */
193 sbit CP1EN = CPT1CN ^ 7; /* COMPARATOR 1 ENABLE */
194 sbit CP1OUT = CPT1CN ^ 6; /* COMPARATOR 1 OUTPUT */
195 sbit CP1RIF = CPT1CN ^ 5; /* COMPARATOR 1 RISING EDGE INTERRUPT */
196 sbit CP1FIF = CPT1CN ^ 4; /* COMPARATOR 1 FALLING EDGE INTERRUPT */
197 sbit CP1HYP1 = CPT1CN ^ 3; /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */
198 sbit CP1HYP0 = CPT1CN ^ 2; /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */
199 sbit CP1HYN1 = CPT1CN ^ 1; /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */
200 sbit CP1HYN0 = CPT1CN ^ 0; /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */
201
202 /* CPT2CN 0x88 */
203 sbit CP2EN = CPT2CN ^ 7; /* COMPARATOR 2 ENABLE */
204 sbit CP2OUT = CPT2CN ^ 6; /* COMPARATOR 2 OUTPUT */
205 sbit CP2RIF = CPT2CN ^ 5; /* COMPARATOR 2 RISING EDGE INTERRUPT */
206 sbit CP2FIF = CPT2CN ^ 4; /* COMPARATOR 2 FALLING EDGE INTERRUPT */
207 sbit CP2HYP1 = CPT2CN ^ 3; /* COMPARATOR 2 POSITIVE HYSTERESIS 1 */
208 sbit CP2HYP0 = CPT2CN ^ 2; /* COMPARATOR 2 POSITIVE HYSTERESIS 0 */
209 sbit CP2HYN1 = CPT2CN ^ 1; /* COMPARATOR 2 NEGATIVE HYSTERESIS 1 */
210 sbit CP2HYN0 = CPT2CN ^ 0; /* COMPARATOR 2 NEGATIVE HYSTERESIS 0 */
211
212 /* SCON0 0x98 */
213 sbit SM00 = SCON0 ^ 7; /* UART 0 MODE 0 */
214 sbit SM10 = SCON0 ^ 6; /* UART 0 MODE 1 */
215 sbit SM20 = SCON0 ^ 5; /* UART 0 MCE */
216 sbit REN0 = SCON0 ^ 4; /* UART 0 RX ENABLE */
217 sbit TB80 = SCON0 ^ 3; /* UART 0 TX BIT 8 */
218 sbit RB80 = SCON0 ^ 2; /* UART 0 RX BIT 8 */
219 sbit TI0 = SCON0 ^ 1; /* UART 0 TX INTERRUPT FLAG */
220 sbit RI0 = SCON0 ^ 0; /* UART 0 RX INTERRUPT FLAG */
221
222 /* SCON1 0x98 */
223 sbit S0MODE = SCON1 ^ 7; /* UART 1 MODE */
224 sbit MCE1 = SCON1 ^ 5; /* UART 1 MCE */
225 sbit REN1 = SCON1 ^ 4; /* UART 1 RX ENABLE */
226 sbit TB81 = SCON1 ^ 3; /* UART 1 TX BIT 8 */
227 sbit RB81 = SCON1 ^ 2; /* UART 1 RX BIT 8 */
228 sbit TI1 = SCON1 ^ 1; /* UART 1 TX INTERRUPT FLAG */
229 sbit RI1 = SCON1 ^ 0; /* UART 1 RX INTERRUPT FLAG */
230
231 /* IE 0xA8 */
232 sbit EA = IE ^ 7; /* GLOBAL INTERRUPT ENABLE */
233 sbit ET2 = IE ^ 5; /* TIMER 2 INTERRUPT ENABLE */
234 sbit ES0 = IE ^ 4; /* UART0 INTERRUPT ENABLE */
235 sbit ET1 = IE ^ 3; /* TIMER 1 INTERRUPT ENABLE */
236 sbit EX1 = IE ^ 2; /* EXTERNAL INTERRUPT 1 ENABLE */
237 sbit ET0 = IE ^ 1; /* TIMER 0 INTERRUPT ENABLE */
238 sbit EX0 = IE ^ 0; /* EXTERNAL INTERRUPT 0 ENABLE */
239
240 /* IP 0xB8 */
241 sbit PT2 = IP ^ 5; /* TIMER 2 PRIORITY */
C51 COMPILER V6.23a C8051F040 12/14/2004 13:09:06 PAGE 5
242 sbit PS = IP ^ 4; /* SERIAL PORT PRIORITY */
243 sbit PT1 = IP ^ 3; /* TIMER 1 PRIORITY */
244 sbit PX1 = IP ^ 2; /* EXTERNAL INTERRUPT 1 PRIORITY */
245 sbit PT0 = IP ^ 1; /* TIMER 0 PRIORITY */
246 sbit PX0 = IP ^ 0; /* EXTERNAL INTERRUPT 0 PRIORITY */
247
248 /* SMB0CN 0xC0 */
249 sbit BUSY = SMB0CN ^ 7; /* SMBUS 0 BUSY */
250 sbit ENSMB = SMB0CN ^ 6; /* SMBUS 0 ENABLE */
251 sbit STA = SMB0CN ^ 5; /* SMBUS 0 START FLAG */
252 sbit STO = SMB0CN ^ 4; /* SMBUS 0 STOP FLAG */
253 sbit SI = SMB0CN ^ 3; /* SMBUS 0 INTERRUPT PENDING FLAG */
254 sbit AA = SMB0CN ^ 2; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
255 sbit SMBFTE = SMB0CN ^ 1; /* SMBUS 0 FREE TIMER ENABLE */
256 sbit SMBTOE = SMB0CN ^ 0; /* SMBUS 0 TIMEOUT ENABLE */
257
258 /* CAN0STA 0xC0 */
259 sbit BOFF = CAN0STA ^ 7; /* Bus Off Status */
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