int.src

2个F040之间的CAN通讯

; .\int.SRC generated from: int.c
; COMPILER INVOKED BY:
;        C:\Keil\C51\BIN\C51.EXE int.c BROWSE DEBUG OBJECTEXTEND SRC(.\int.SRC)

$NOMOD51

NAME	INT

CCF2	BIT	0D8H.2
EWARN	BIT	0C0H.6
TB80	BIT	098H.3
SPI0CKR	DATA	09DH
CCF3	BIT	0D8H.3
TB81	BIT	098H.3
CAN0TST	DATA	0DBH
P0	DATA	080H
SPIEN	BIT	0F8H.0
CCF4	BIT	0D8H.4
SM00	BIT	098H.7
P1	DATA	090H
CCF5	BIT	0D8H.5
AA	BIT	0C0H.2
SM10	BIT	098H.6
WDTCN	DATA	0FFH
P2	DATA	0A0H
SM20	BIT	098H.5
ADC0CF	DATA	0BCH
P3	DATA	0B0H
AC	BIT	0D0H.6
P4	DATA	0C8H
LEC0	BIT	0C0H.0
EIE1	DATA	0E6H
P5	DATA	0D8H
ADC2CF	DATA	0BCH
LEC1	BIT	0C0H.1
EA	BIT	0A8H.7
P6	DATA	0E8H
EIE2	DATA	0E7H
LEC2	BIT	0C0H.2
MCE1	BIT	098H.5
P7	DATA	0F8H
PSCTL	DATA	08FH
CANINIT	BIT	0F8H.0
CF	BIT	0D8H.7
ADC0CN	DATA	0E8H
DAC0CN	DATA	0D4H
SFRPAGE	DATA	084H
DAC1CN	DATA	0D4H
P0MDOUT	DATA	0A4H
ADC2CN	DATA	0E8H
P1MDOUT	DATA	0A5H
IE	DATA	0A8H
P2MDOUT	DATA	0A6H
AMX0PRT	DATA	0BDH
P3MDOUT	DATA	0A7H
EIP1	DATA	0F6H
P4MDOUT	DATA	09CH
TXBMT	BIT	0F8H.1
EIP2	DATA	0F7H
P5MDOUT	DATA	09DH
PCA0CPH0	DATA	0FCH
P6MDOUT	DATA	09EH
PCA0CPH1	DATA	0FEH
P7MDOUT	DATA	09FH
PCA0CPH2	DATA	0EAH
CANTEST	BIT	0F8H.7
CR	BIT	0D8H.6
CAN0CN	DATA	0F8H
PCA0CPH3	DATA	0ECH
EXF2	BIT	0C8H.6
REN0	BIT	098H.4
PCA0CPL0	DATA	0FBH
PCA0CPH4	DATA	0EEH
EMI0CF	DATA	0A3H
SFRPGCN	DATA	096H
EXF3	BIT	0C8H.6
REN1	BIT	098H.4
PCA0CPL1	DATA	0FDH
PCA0CPH5	DATA	0E2H
PCA0CPM0	DATA	0DAH
PCA0MD	DATA	0D9H
PCA0CN	DATA	0D8H
ADC2GT	DATA	0C4H
EXF4	BIT	0C8H.6
PCA0CPL2	DATA	0E9H
PCA0CPM1	DATA	0DBH
PCA0CPL3	DATA	0EBH
PCA0CPM2	DATA	0DCH
IP	DATA	0B8H
CP0FIF	BIT	088H.4
PCA0CPL4	DATA	0EDH
PCA0CPM3	DATA	0DDH
CP1FIF	BIT	088H.4
PCA0CPL5	DATA	0E1H
PCA0CPM4	DATA	0DEH
CY	BIT	0D0H.7
SI	BIT	0C0H.3
CP2FIF	BIT	088H.4
PCA0CPM5	DATA	0DFH
ADC2LT	DATA	0C6H
XBR0	DATA	0E1H
SADEN0	DATA	0B9H
BOFF	BIT	0C0H.7
XBR1	DATA	0E2H
EMI0CN	DATA	0A2H
CANCCE	BIT	0F8H.6
XBR2	DATA	0E3H
XBR3	DATA	0E4H
REF0CN	DATA	0D1H
SADDR0	DATA	0A9H
AMX0CF	DATA	0BAH
SADDR1	DATA	0A9H
AD0INT	BIT	0E8H.5
HVA0CN	DATA	0D6H
RCAP2H	DATA	0CBH
SFRLAST	DATA	086H
PS	BIT	0B8H.4
RCAP3H	DATA	0CBH
AMX2CF	DATA	0BAH
SP	DATA	081H
AD2INT	BIT	0E8H.5
RCAP4H	DATA	0CBH
EMI0TC	DATA	0A1H
OV	BIT	0D0H.2
SMB0CN	DATA	0C0H
CP0RIF	BIT	088H.5
CAN0DATH	DATA	0D9H
RCAP2L	DATA	0CAH
CANEIE	BIT	0F8H.3
MODF	BIT	0F8H.5
CP1RIF	BIT	088H.5
RCAP3L	DATA	0CAH
CP2RIF	BIT	088H.5
RCAP4L	DATA	0CAH
SMB0CR	DATA	0CFH
S0MODE	BIT	098H.7
CAN0DATL	DATA	0D8H
CPT0MD	DATA	089H
CPT0CN	DATA	088H
CANDAR	BIT	0F8H.5
P1MDIN	DATA	0ADH
CPT1MD	DATA	089H
CPT1CN	DATA	088H
P2MDIN	DATA	0AEH
CPT2MD	DATA	089H
CPT2CN	DATA	088H
P3MDIN	DATA	0AFH
SFRNEXT	DATA	085H
SPI0CN	DATA	0F8H
TMR2CF	DATA	0C9H
TMR3CF	DATA	0C9H
PCON	DATA	087H
TMR4CF	DATA	0C9H
SPIF	BIT	0F8H.7
CANSIE	BIT	0F8H.2
TMOD	DATA	089H
TCON	DATA	088H
WCOL	BIT	0F8H.6
NSSMD0	BIT	0F8H.2
AMX0SL	DATA	0BBH
NSSMD1	BIT	0F8H.3
TMR2CN	DATA	0C8H
TMR3CN	DATA	0C8H
AMX2SL	DATA	0BBH
TMR4CN	DATA	0C8H
CP0OUT	BIT	088H.6
CP1OUT	BIT	088H.6
IE0	BIT	088H.1
CP2OUT	BIT	088H.6
IE1	BIT	088H.3
OSCICL	DATA	08BH
CLKSEL	DATA	097H
B	DATA	0F0H
DAC0H	DATA	0D3H
ADC0H	DATA	0BFH
OSCICN	DATA	08AH
DAC1H	DATA	0D3H
SMBFTE	BIT	0C0H.1
BUSY	BIT	0C0H.7
RXOK	BIT	0C0H.4
DAC0L	DATA	0D2H
ADC0L	DATA	0BEH
DAC1L	DATA	0D2H
TXOK	BIT	0C0H.3
ACC	DATA	0E0H
ES0	BIT	0A8H.4
AD0EN	BIT	0E8H.7
CT2	BIT	0C8H.1
ET0	BIT	0A8H.1
CT3	BIT	0C8H.1
ET1	BIT	0A8H.3
TF0	BIT	088H.5
AD2EN	BIT	0E8H.7
CT4	BIT	0C8H.1
ET2	BIT	0A8H.5
RI0	BIT	098H.0
TF1	BIT	088H.7
TF2	BIT	0C8H.7
SMBTOE	BIT	0C0H.0
RI1	BIT	098H.0
TH0	DATA	08CH
TF3	BIT	0C8H.7
EX0	BIT	0A8H.0
TI0	BIT	098H.1
IT0	BIT	088H.0
PCA0H	DATA	0FAH
TH1	DATA	08DH
TF4	BIT	0C8H.7
EX1	BIT	0A8H.2
TI1	BIT	098H.1
IT1	BIT	088H.2
P	BIT	0D0H.0
OSCXCN	DATA	08CH
TL0	DATA	08AH
PCA0L	DATA	0F9H
TL1	DATA	08BH
PT0	BIT	0B8H.1
RS0	BIT	0D0H.3
PT1	BIT	0B8H.3
RS1	BIT	0D0H.4
PT2	BIT	0B8H.5
TR0	BIT	088H.4
AD0TM	BIT	0E8H.6
CP0EN	BIT	088H.7
TR1	BIT	088H.6
TR2	BIT	0C8H.2
PX0	BIT	0B8H.0
CP1EN	BIT	088H.7
AD2TM	BIT	0E8H.6
TR3	BIT	0C8H.2
PX1	BIT	0B8H.2
CP2EN	BIT	088H.7
TR4	BIT	0C8H.2
CAN0ADR	DATA	0DAH
DPH	DATA	083H
ADC0GTH	DATA	0C5H
DPL	DATA	082H
CANIE	BIT	0F8H.1
ADC0GTL	DATA	0C4H
SBUF0	DATA	099H
CANIF	BIT	0F8H.4
ADC0LTH	DATA	0C7H
SBUF1	DATA	099H
EXEN2	BIT	0C8H.3
RSTSRC	DATA	0EFH
FLACL	DATA	0B7H
EXEN3	BIT	0C8H.3
CPRL2	BIT	0C8H.0
CP0HYN0	BIT	088H.0
SCON0	DATA	098H
EXEN4	BIT	0C8H.3
CPRL3	BIT	0C8H.0
CP1HYN0	BIT	088H.0
CP0HYN1	BIT	088H.1
SCON1	DATA	098H
CPRL4	BIT	0C8H.0
CP2HYN0	BIT	088H.0
CP1HYN1	BIT	088H.1
CP0HYP0	BIT	088H.2
ADC0LTL	DATA	0C6H
CP2HYN1	BIT	088H.1
CP1HYP0	BIT	088H.2
CP0HYP1	BIT	088H.3
STA	BIT	0C0H.5
CP2HYP0	BIT	088H.2
CP1HYP1	BIT	088H.3
CP2HYP1	BIT	088H.3
SMB0ADR	DATA	0C3H
CAN0STA	DATA	0C0H
SSTA0	DATA	091H
SMB0DAT	DATA	0C2H
TMR2H	DATA	0CDH
SPI0CFG	DATA	09AH
TMR3H	DATA	0CDH
CKCON	DATA	08EH
TMR4H	DATA	0CDH
RXOVRN	BIT	0F8H.4
TMR2L	DATA	0CCH
TMR3L	DATA	0CCH
TMR4L	DATA	0CCH
F0	BIT	0D0H.5
FLSCL	DATA	0B7H
AD0CM0	BIT	0E8H.2
F1	BIT	0D0H.1
STO	BIT	0C0H.4
ENSMB	BIT	0C0H.6
AD0CM1	BIT	0E8H.3
SPI0DAT	DATA	09BH
AD2CM0	BIT	0E8H.0
AD2CM1	BIT	0E8H.1
AD0WINT	BIT	0E8H.1
AD2CM2	BIT	0E8H.2
AD0BUSY	BIT	0E8H.4
PSW	DATA	0D0H
ADC2	DATA	0BEH
AD2WINT	BIT	0E8H.3
AD2BUSY	BIT	0E8H.4
CCF0	BIT	0D8H.0
RB80	BIT	098H.2
SMB0STA	DATA	0C1H
CCF1	BIT	0D8H.1
EPASS	BIT	0C0H.5
RB81	BIT	098H.2
?PR?SYSCLK_Init?INT  SEGMENT CODE 
?PR?PORT_Init?INT    SEGMENT CODE 
?PR?INT_Init?INT     SEGMENT CODE 
?PR?CAN_Init?INT     SEGMENT CODE 
?PR?_CAN_Transmit_Init?INT               SEGMENT CODE 
?PR?_CAN_Receive_Init?INT                SEGMENT CODE 
?PR?Timer_Init?INT   SEGMENT CODE 
?PR?_CAN_send?INT    SEGMENT CODE 
?DT?_CAN_send?INT    SEGMENT DATA OVERLAYABLE 
?PR?_CAN_receive?INT SEGMENT CODE 
?DT?_CAN_receive?INT SEGMENT DATA OVERLAYABLE 
?PR?_remote_rqst_int?INT                 SEGMENT CODE 
?PR?_remote_rqst?INT SEGMENT CODE 
?C_INITSEG           SEGMENT CODE 
?XD?INT              SEGMENT XDATA 
	EXTRN	CODE (?C?CLDOPTR)
	EXTRN	CODE (?C?CSTOPTR)
	PUBLIC	ss
	PUBLIC	rr?
	PUBLIC	_remote_rqst
	PUBLIC	_remote_rqst_int
	PUBLIC	_CAN_receive
	PUBLIC	_CAN_send
	PUBLIC	Timer_Init
	PUBLIC	_CAN_Receive_Init
	PUBLIC	_CAN_Transmit_Init
	PUBLIC	CAN_Init
	PUBLIC	INT_Init
	PUBLIC	PORT_Init
	PUBLIC	SYSCLK_Init

	RSEG  ?DT?_CAN_send?INT
?_CAN_send?BYTE:
          p?747:   DS   3

	RSEG  ?DT?_CAN_receive?INT
?_CAN_receive?BYTE:
          p?850:   DS   3

	RSEG  ?XD?INT
            rr?:   DS   8
             ss:   DS   8

	RSEG  ?C_INITSEG
	DB	048H
	DW	ss
	DB	011H
	DB	022H
	DB	033H
	DB	044H
	DB	055H
	DB	066H
	DB	077H
	DB	088H

	DB	048H
	DW	rr?
	DB	000H
	DB	000H
	DB	000H
	DB	000H
	DB	000H
	DB	000H
	DB	000H
	DB	000H

; #include "c8051f040.h"
; #include "can.h"
; 
; extern unsigned char   DO_Address;
; extern unsigned char  temp1,temp2;
; extern unsigned char  DO_Control_Data_New0,DO_Control_Data_New1;
; 
; /*
; union u_int
; {
;   unsigned int id_int;
;   struct {unsigned char id_H;unsigned char id_L;} id_char;
; };
; 
; xdata union u_int id_tx,id_rx;  */
; xdata unsigned char ss[8]={0x11,0x22,0x33,0x44,0x55,0x66,0x77,0x88};
; xdata unsigned char rr[8]={0,0,0,0,0,0,0,0};
; 
; //-----------------------------------------------------------------------------
; // SYSCLK_Init
; //-----------------------------------------------------------------------------
; void SYSCLK_Init (void) 

	RSEG  ?PR?SYSCLK_Init?INT
SYSCLK_Init:
			; SOURCE LINE # 22
; {
			; SOURCE LINE # 23
;   SFRPAGE = 0xF;
			; SOURCE LINE # 24
	MOV  	SFRPAGE,#0FH
;   OSCXCN |= 0x67;					   //Running at 22.1184MHz.	
			; SOURCE LINE # 25
	ORL  	OSCXCN,#067H
?C0001:
;   while (!((OSCXCN & 0x80) == 0x80));
			; SOURCE LINE # 26
	MOV  	A,OSCXCN
	JNB  	ACC.7,?C0003
	SETB 	C
	SJMP 	?C0004
?C0003:
	CLR  	C
?C0004:
	JNC  	?C0001
?C0002:
;   CLKSEL |= 0x01;
			; SOURCE LINE # 27
	ORL  	CLKSEL,#01H
; }
			; SOURCE LINE # 28
	RET  	
; END OF SYSCLK_Init

;  
; //-----------------------------------------------------------------------------
; // PORT_Init
; //-----------------------------------------------------------------------------
; void PORT_Init (void) 

	RSEG  ?PR?PORT_Init?INT
PORT_Init:
			; SOURCE LINE # 33
; {
			; SOURCE LINE # 34
;   SFRPAGE = 0xF;
			; SOURCE LINE # 35
	MOV  	SFRPAGE,#0FH
; XBR1 |= 0x00;
			; SOURCE LINE # 36
;   XBR1 |= 0x04;              //INT0 Routed To Port Pin
			; SOURCE LINE # 37
	ORL  	XBR1,#04H
;   XBR2 |= 0x40;              //If crossbar is disabled, all ports are in input mode.  
			; SOURCE LINE # 38
	ORL  	XBR2,#040H
;   XBR3 |= 0x80;              //CTX pin's output mode is configured as push-pull.
			; SOURCE LINE # 39
	ORL  	XBR3,#080H
; P0MDOUT = 0x00;
			; SOURCE LINE # 40
	CLR  	A
	MOV  	P0MDOUT,A
; P1MDIN =0xFF;
			; SOURCE LINE # 41
	MOV  	P1MDIN,#0FFH
;  // P4MDOUT = 0x03;            //CANLED and ENABLE
;  // P5MDOUT = 0x00;            //OUTPUT CONTROL PORT
;  // P6MDOUT = 0x00;            //OUTPUT CONTROL PORT
; }
			; SOURCE LINE # 45
	RET  	
; END OF PORT_Init

; 
; //-----------------------------------------------------------------------------
; // INT_Init
; // Interrupts By Priority : INT0 > CAN0
; //-----------------------------------------------------------------------------
; void INT_Init (void) 

	RSEG  ?PR?INT_Init?INT
INT_Init:
			; SOURCE LINE # 51
; {
			; SOURCE LINE # 52
; //  IE   |= 0x03;              //INT0 Interrupt Enabled        
;                              //Timer0 Interrupt Enabled
; //  IE   |= 0x01;              //INT0 Interrupt Enabled
;   EIE2 |= 0x20;              //CAN0 Interrupt Enabled
			; SOURCE LINE # 56
	ORL  	EIE2,#020H
; }
			; SOURCE LINE # 57
	RET  	
; END OF INT_Init

;