hal_diag.c

ecos在9200上redboot实现

//=============================================================================
//
//      hal_diag.c
//
//      HAL diagnostic output code
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    Jiun-Shian H. <[e-mail]>
// Contributors: Jiun-Shian H. <[e-mail]>
// Date:         2005-08-10
// Purpose:      HAL diagnostic output
// Description:  Implementations of HAL diagnostic output support.
//
//####DESCRIPTIONEND####
//
//=============================================================================

#include <pkgconf/hal.h>
#include CYGBLD_HAL_VARIANT_H           // Variant specific configuration
#include CYGBLD_HAL_PLATFORM_H          // Platform specific configuration

#include <cyg/infra/cyg_type.h>         // base types
#include <cyg/infra/cyg_trac.h>         // tracing macros
#include <cyg/infra/cyg_ass.h>          // assertion macros

#include <cyg/hal/hal_arch.h>           // basic machine info
#include <cyg/hal/hal_intr.h>           // interrupt macros
#include <cyg/hal/hal_io.h>             // IO macros
#include <cyg/hal/hal_diag.h>
#include <cyg/hal/drv_api.h>
#include <cyg/hal/hal_if.h>             // interface API
#include <cyg/hal/hal_misc.h>           // Helper functions
#include <cyg/hal/at91rm9200.h>         // platform definitions

//-----------------------------------------------------------------------------
typedef struct {
    cyg_uint32 base;
    cyg_int32 msec_timeout;
    int isr_vector;
} channel_data_t;

/* Using PA31/DTXD, PA30/DRXD */
static channel_data_t at91rm9200_ser_channels[1] = {
/*    {(cyg_uint32)0xFFFFF200, 1000, 0X01} */
      {(cyg_uint32)BASE_DBGU, 1000, CYGNUM_HAL_INTERRUPT_SYS}
};


//-----------------------------------------------------------------------------

static void
cyg_hal_plf_serial_init_channel(void* __ch_data)
{
    cyg_uint32 base = ((channel_data_t*)__ch_data)->base;

    unsigned int baud_value = 0;
    unsigned int main_clock = 0;
    unsigned int master_clock = 0;
    unsigned int baud_rate = CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD;
    unsigned int val, pll;

    /*
    ** Enable pins to be drived by peripheral,
    ** Set PA30, PA31 as debug UART.
    ** Select peripheral A.
    */
    HAL_WRITE_UINT32((BASE_PIOA+PIO_ASR),
                     (C_PA31_DTXD | C_PA30_DRXD));
    HAL_WRITE_UINT32((BASE_PIOA+PIO_BSR), 0);
    /* Disables the PIO from controlling the corresponding pin
      (enables peripheral control of the pin). */
    HAL_WRITE_UINT32((BASE_PIOA+PIO_PDR),
                     (C_PA31_DTXD | C_PA30_DRXD));

    /* Disable interrupt */
    HAL_WRITE_UINT32((base+DBGU_IDR), 0xFFFFFFFF);

    /* Reset receiver and transmitter */
    HAL_WRITE_UINT32((base+DBGU_CR),
                     (C_US_RSTRX | C_US_RSTTX | C_US_RXDIS | C_US_TXDIS));

    HAL_READ_UINT32((BASE_PMC+PMC_MCKR), val);
    switch (val & 0x03)
      {
        /* Slow clock */
        case 0x00:
          main_clock = 32768;
          break;

        /* Main clock */
        case 0x01:
          main_clock = 18432000;
          break;

        /* PLL-A */
        case 0x02:
          HAL_READ_UINT32((BASE_PMC+PMC_CKGR_PLLAR), pll);
          main_clock = 18432000 * ((pll & 0x7FF0000) >> 16) / (pll & 0xFF);
          break;

        /* PLL-B */
        case 0x03:
          HAL_READ_UINT32((BASE_PMC+PMC_CKGR_PLLBR), pll);
          main_clock = 18432000 * ((pll & 0x7FF0000) >> 16) / (pll & 0xFF);
          break;
      }
    switch ((val & 0x1C) >> 2)
      {
        /* Selected clock */
        case 0x00:
        /* Reserved */
        case 0x07:
          break;

        /* Selected clock divided by 2 */
        case 0x01:
          main_clock /= 2;
          break;

        /* Selected clock divided by 4 */
        case 0x02:
          main_clock /= 4;
          break;

        /* Selected clock divided by 8 */
        case 0x03:
          main_clock /= 8;
          break;

        /* Selected clock divided by 16 */
        case 0x04:
          main_clock /= 16;
          break;

        /* Selected clock divided by 32 */
        case 0x05:
          main_clock /= 32;
          break;

        /* Selected clock divided by 64 */
        case 0x06:
          main_clock /= 64;
          break;
      }
    switch (val & 0x300)
      {
        /* The Master Clock and the Processor Clock are the same. */
        case 0x000:
          master_clock = main_clock;
          break;

        /* The Master Clock and the Processor Clock are the same. */
        case 0x100:
          master_clock = main_clock / 2;
          break;

        /* The Processor Clock is three times faster than the Master Clock. */
        case 0x200:
          master_clock = main_clock / 3;
          break;

        /* The Processor Clock is four times faster than the Master Clock. */
        case 0x300:
          master_clock = main_clock / 4;
          break;
      }

    /* Define the baud rate divisor register, (round) */
    baud_value = ((master_clock*10)/(baud_rate * 16));
    if ((baud_value % 10) >= 5)
        baud_value = (baud_value / 10) + 1;
    else
        baud_value /= 10;

    HAL_WRITE_UINT32((base+DBGU_BRGR), baud_value);

    /* Write the Timeguard Register */
    HAL_WRITE_UINT32((base+DBGU_TTGR), 0);

    /* Clear Transmit and Receive Counters,
       Disable TX and RX reset transfer descriptors,
       re-enable RX and TX */
    /* Disable the RX and TX PDC transfer requests */
    HAL_WRITE_UINT32((base+DBGU_PTCR), C_PDC_RXTDIS);
    HAL_WRITE_UINT32((base+DBGU_PTCR), C_PDC_TXTDIS);

    /* Reset all Counter register Next buffer first */
    HAL_WRITE_UINT32((base+DBGU_TNPR), 0);
    HAL_WRITE_UINT32((base+DBGU_TNCR), 0);

    HAL_WRITE_UINT32((base+DBGU_RNPR), 0);
    HAL_WRITE_UINT32((base+DBGU_RNCR), 0);

    HAL_WRITE_UINT32((base+DBGU_TPR), 0);
    HAL_WRITE_UINT32((base+DBGU_TCR), 0);

    HAL_WRITE_UINT32((base+DBGU_RPR), 0);
    HAL_WRITE_UINT32((base+DBGU_RCR), 0);

    /* Enable the RX and TX PDC transfer requests */
    HAL_WRITE_UINT32((base+DBGU_PTCR), C_PDC_RXTEN);
    HAL_WRITE_UINT32((base+DBGU_PTCR), C_PDC_TXTEN);

    /* Define the USART mode */
    /* (USART) Normal, 1 stop bit, No Parity, Character Length: 8 bits, Clock */
    HAL_WRITE_UINT32((base+DBGU_MR), (((unsigned int) 0x0) +
                                      ((unsigned int) 0x0 << 12) +
                                      ((unsigned int) 0x4 <<  9) +
                                      ((unsigned int) 0x3 <<  6) +
                                      ((unsigned int) 0x0 <<  4) ));

    /* Enable Transmitter */
    HAL_WRITE_UINT32((base+DBGU_CR), C_US_TXEN);
    /* Enable Receiver */
    HAL_WRITE_UINT32((base+DBGU_CR), C_US_RXEN);
}

void
cyg_hal_plf_serial_putc(void* __ch_data, char c)
{
    cyg_uint32 base = ((channel_data_t*)__ch_data)->base;
    cyg_uint32 status;
    CYGARC_HAL_SAVE_GP();

    // Wait for Tx FIFO not full
    do
    {
        HAL_READ_UINT32((base+DBGU_SR), status);
    }
    while (!(status & C_US_TXRDY)) ;

    //UART TX data register
    HAL_WRITE_UINT8((base+DBGU_THR), c);

    CYGARC_HAL_RESTORE_GP();
}

static cyg_bool
cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
{
    cyg_uint32 base = ((channel_data_t*)__ch_data)->base;
    cyg_uint32 status;

    /* Using PA31/DTXD, PA30/DRXD */
    base = 0xFFFFF200;

    HAL_READ_UINT32((base+DBGU_SR), status);
    if (status & 0x01)
    {
        HAL_READ_UINT8((base+DBGU_RHR), *ch);
        return true;
    }

    return false;
}

cyg_uint8
cyg_hal_plf_serial_getc(void* __ch_data)
{
    cyg_uint8 ch;
    CYGARC_HAL_SAVE_GP();

    while (!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));

    CYGARC_HAL_RESTORE_GP();
    return ch;
}

static void
cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
                         cyg_uint32 __len)
{
    CYGARC_HAL_SAVE_GP();

    while (__len-- > 0)
        cyg_hal_plf_serial_putc(__ch_data, *__buf++);

    CYGARC_HAL_RESTORE_GP();
}

static void
cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
{
    CYGARC_HAL_SAVE_GP();

    while (__len-- > 0)
        *__buf++ = cyg_hal_plf_serial_getc(__ch_data);

    CYGARC_HAL_RESTORE_GP();
}

cyg_bool
cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
{
    int delay_count;
    channel_data_t* chan = (channel_data_t*)__ch_data;
    cyg_bool res;
    CYGARC_HAL_SAVE_GP();

    delay_count = chan->msec_timeout * 10; // delay in .1 ms steps

    for (;;) {
        res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
        if (res || 0 == delay_count--)
            break;

        CYGACC_CALL_IF_DELAY_US(100);
    }

    CYGARC_HAL_RESTORE_GP();
    return res;
}

static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
    static int irq_state = 0;
    channel_data_t* chan = (channel_data_t*)__ch_data;
    int ret = 0;
    CYGARC_HAL_SAVE_GP();

    switch (__func) {
    case __COMMCTL_IRQ_ENABLE:
        irq_state = 1;
        HAL_INTERRUPT_UNMASK(chan->isr_vector);
        break;
    case __COMMCTL_IRQ_DISABLE:
        ret = irq_state;
        irq_state = 0;
        HAL_INTERRUPT_MASK(chan->isr_vector);
        break;
    case __COMMCTL_DBG_ISR_VECTOR:
        ret = chan->isr_vector;
        break;
    case __COMMCTL_SET_TIMEOUT:
    {
        va_list ap;

        va_start(ap, __func);

        ret = chan->msec_timeout;
        chan->msec_timeout = va_arg(ap, cyg_uint32);

        va_end(ap);
    }
    default:
        break;
    }
    CYGARC_HAL_RESTORE_GP();
    return ret;
}

static int
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
                       CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
    int res = 0;
    channel_data_t* chan = (channel_data_t*)__ch_data;
    char c;
    cyg_uint32 lsr;
    CYGARC_HAL_SAVE_GP();

    cyg_drv_interrupt_acknowledge(chan->isr_vector);

    *__ctrlc = 0;
/*
    HAL_READ_UINT32(chan->base+OFS_UFSTAT, lsr);
*/
/*
    if (lsr & 0x0f)
    {
        HAL_READ_UINT8(chan->base+OFS_URXH, c);
        if( cyg_hal_is_break( &c , 1 ) )
*/
            *__ctrlc = 1;

        res = CYG_ISR_HANDLED;
/*
    }
*/

    CYGARC_HAL_RESTORE_GP();
    return res;
}

static void
cyg_hal_plf_serial_init(void)
{
    hal_virtual_comm_table_t* comm;
    int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);

    // Disable interrupts.
    HAL_INTERRUPT_MASK(at91rm9200_ser_channels[0].isr_vector);

#if 0 /* By Internal ROMBoot */

#define __READ_UINT32( _register_ ) *((volatile CYG_WORD32 *)(_register_))
    //Unmask UART0/1 RX interrupt
    HAL_WRITE_UINT32(INTSUBMSK, __READ_UINT32(INTSUBMSK) & ~(BIT_SUB_RXD0|BIT_SUB_RXD1));

#endif /* 0/1 */

    // Init channels
    cyg_hal_plf_serial_init_channel(&at91rm9200_ser_channels[0]);

    // Setup procs in the vector table

    // Set channel 0
    CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
    comm = CYGACC_CALL_IF_CONSOLE_PROCS();
    CYGACC_COMM_IF_CH_DATA_SET(*comm, &at91rm9200_ser_channels[0]);
    CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
    CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
    CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
    CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
    CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
    CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
    CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);

    // Restore original console
    CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}

void
cyg_hal_plf_comms_init(void)
{
    static int initialized = 0;

    if (initialized)
        return;

    initialized = 1;

    cyg_hal_plf_serial_init();
}

void
hal_diag_led(int mask)
{
  /* ToDo */
}


//-----------------------------------------------------------------------------
// End of hal_diag.c