at91rm9200_misc.c

ecos在9200上redboot实现

    //Binary :  10     10     10      10
    HAL_WRITE_UINT32(GPECON, 0xaaaaaaaa);
    HAL_WRITE_UINT32(GPEUP, 0xffff);     // The pull up function is disabled GPE[15:0]

    //*** PORT F GROUP
    //Ports  : GPF7   GPF6   GPF5   GPF4      GPF3     GPF2  GPF1   GPF0
    //Signal : nLED_8 nLED_4 nLED_2 nLED_1 nIRQ_PCMCIA EINT2 KBDINT EINT0
    //Setting: Output Output Output Output    EINT3    EINT2 EINT1  EINT0
    //Binary :  01      01     01     01       10       10    10     10
    HAL_WRITE_UINT32(GPFCON, 0x55aa);
    HAL_WRITE_UINT32(GPFUP, 0xff);       // The pull up function is disabled GPF[7:0]

    //*** PORT G GROUP
    //Ports  : GPG15 GPG14 GPG13 GPG12 GPG11    GPG10    GPG9     GPG8     GPG7      GPG6
    //Signal : nYPON  YMON nXPON XMON  EINT19 DMAMODE1 DMAMODE0 DMASTART KBDSPICLK KBDSPIMOSI
    //Setting: nYPON  YMON nXPON XMON  EINT19  Output   Output   Output   SPICLK1    SPIMOSI1
    //Binary :   11    11   11    11    10      01        01       01       11         11
    //-----------------------------------------------------------------------------------------
    //Ports  :    GPG5       GPG4    GPG3    GPG2    GPG1    GPG0
    //Signal : KBDSPIMISO LCD_PWREN EINT11 nSS_SPI IRQ_LAN IRQ_PCMCIA
    //Setting:  SPIMISO1  LCD_PWRDN EINT11   nSS0   EINT9    EINT8
    //Binary :     11         11      10      11     10       10
    HAL_WRITE_UINT32(GPGCON, 0xff95ffba);
    HAL_WRITE_UINT32(GPGUP, 0xffff);     // The pull up function is disabled GPG[15:0]

    //*** PORT H GROUP
    //Ports  :  GPH10    GPH9  GPH8 GPH7  GPH6  GPH5 GPH4 GPH3 GPH2 GPH1  GPH0
    //Signal : CLKOUT1 CLKOUT0 UCLK nCTS1 nRTS1 RXD1 TXD1 RXD0 TXD0 nRTS0 nCTS0
    //Binary :   10      10     10   11    11    10   10   10   10   10    10
    HAL_WRITE_UINT32(GPHCON, 0x2afaaa);
    HAL_WRITE_UINT32(GPHUP, 0x7ff);      // The pull up function is disabled GPH[10:0]

    //External interrupts will be falling edge triggered.
    HAL_WRITE_UINT32(EXTINT0, 0x22222222);    // EINT[7:0]
    HAL_WRITE_UINT32(EXTINT1, 0x22222222);    // EINT[15:8]
    HAL_WRITE_UINT32(EXTINT2, 0x22222222);    // EINT[23:16]
#endif /* 0/1 */
}

void
plf_hardware_init(void)
{
#if 0
    unsigned int val;

    /* Set PLL */
    /* Set and Using PLLA[180MHz], MCK[60Mhz] */
#define AT91C_PLLA_VALUE  0x2026BE04	// crystal= 18.432MHz

    HAL_WRITE_UINT32((BASE_PMC+PMC_CKGR_PLLAR), AT91C_PLLA_VALUE);
    while (1)
      {
        HAL_READ_UINT32((BASE_PMC+PMC_SR), val);
        if ((val & C_PMC_LOCKA) == 1)
          {
            /* PLL A is locked. */
            break;
          }
      }
    val = 0;
    HAL_WRITE_UINT32((BASE_PMC+PMC_MCKR), 0x202);
    while (val++ < 50000)
    	;
#endif /* 0/1 */

#if 0
    /* Mask all interrupt */

    /* I/O Ports */
    port_init();

#endif /* 0/1 */

    // Initialize real-time clock (for delays, etc, even if kernel doesn't use it)
    hal_clock_initialize(CYGNUM_HAL_RTC_PERIOD);
}

// -------------------------------------------------------------------------
// Use system clock
void
hal_clock_initialize(cyg_uint32 period)
{
  cyg_uint32 val;

  /* Disable all timer interrupts */
  val = (C_ST_PITS | C_ST_WDOVF |
         C_ST_RTTINC | C_ST_ALMS);
  HAL_WRITE_UINT32((BASE_ST+ST_IDR), val);

  /* Clear any pending interrupts, read and clear */
  HAL_READ_UINT32((BASE_ST+ST_SR), val);

  /* Set initial alarm to 0 */
  HAL_WRITE_UINT32((BASE_ST+ST_RTAR), 0);

  /* Real time counter incremented every 30.51758 microseconds (1/32768KHz)*/
#define RTT_PERIOD  (30)
  HAL_WRITE_UINT32((BASE_ST+ST_RTMR), 1);

/* Definitions from Linux */
#define AT91C_SLOW_CLOCK  (SCLK)   /* slow clock */

#define HZ                (100)
#define CLOCK_TICK_RATE   (AT91C_SLOW_CLOCK)
#define LATCH             ((CLOCK_TICK_RATE + HZ/2) / HZ)

  /* Set Period Interval timer */
  HAL_WRITE_UINT32((BASE_ST+ST_PIMR), LATCH);

  /* Enable Period Interval Timer interrupt */
  HAL_WRITE_UINT32((BASE_ST+ST_IER), C_ST_PITS);

}

// This routine is called during a clock interrupt.
void
hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
{
    // Do nothing
}

/*
 * The ST_CRTR is updated asynchronously to the master clock.  It is therefore
 *  necessary to read it twice (with the same value) to ensure accuracy.
 */
static inline unsigned long
read_CRTR(void)
{
  volatile unsigned long x1, x2;

  do
    {
      HAL_WRITE_UINT32((BASE_ST+ST_CRTR), x1);
      HAL_WRITE_UINT32((BASE_ST+ST_CRTR), x2);
    }
  while (x1 != x2);

  return x1;
}


// Read the current value of the clock, returning the number of hardware
// "ticks" that have occurred (i.e. how far away the current value is from
// the start)
void
hal_clock_read(cyg_uint32 *pvalue)
{
#if 1
    cyg_int32 clock_val;

    // Read Timer's current value
    clock_val = read_CRTR();

    // Note: counter is only 20 bits
    // and increase.
//    *pvalue = (clock_val & 0xFFFFF) - CYGNUM_HAL_RTC_PERIOD;
    *pvalue = (clock_val & 0xFFFFF);
#else
  *pvalue = 0;
#endif /* 0/1 */
}


// Delay for some number of micro-seconds
void
hal_delay_us(cyg_int32 usecs)
{
#if 0
  cyg_uint32 wait;
  volatile cyg_uint32 old_crtr;
  volatile cyg_uint32 new_crtr;

  if (usecs < RTT_PERIOD)
    {
      wait = 1;
    }
  else
    {
      // FIXME: round it
      wait = usecs / RTT_PERIOD;
    }
  old_crtr = read_CRTR();
  while (1)
    {
      new_crtr = read_CRTR();
      if (new_crtr > old_crtr)
        {
          if ((new_crtr - old_crtr) > wait)
            { break; }
        }
      else
        {
          if ((0xFFFFF + new_crtr - old_crtr) > wait)
            { break; }
        }
    }
#endif /* 0/1 */
}

// -------------------------------------------------------------------------

// This routine is called to respond to a hardware interrupt (IRQ).  It
// should interrogate the hardware and return the IRQ vector number.
int
hal_IRQ_handler(void)
{
#if 0
    cyg_uint32 ior;

    HAL_READ_UINT32(INTOFFSET, ior);
    return (int)ior;
#endif /* 0/1 */

    return CYGNUM_HAL_INTERRUPT_NONE;
}

//----------------------------------------------------------------------------
// Interrupt control

void
hal_interrupt_mask(int vector)
{

    CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
               vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");

    //* Disable the interrupt on the interrupt controller (Write-Only)
    HAL_WRITE_UINT32((BASE_AIC+AIC_IDCR), (cyg_uint32)vector);

    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
    HAL_WRITE_UINT32((BASE_AIC+AIC_ICCR), (cyg_uint32)vector);
}

void
hal_interrupt_unmask(int vector)
{
    CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
               vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
    //* Enable the interrupt on the interrupt controller
    HAL_WRITE_UINT32((BASE_AIC+AIC_IECR), (cyg_uint32)vector);
}

void
hal_interrupt_acknowledge(int vector)
{
    cyg_uint32 ipr;

    CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
               vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");

    HAL_READ_UINT32((BASE_AIC+AIC_EOICR), ipr);
    HAL_WRITE_UINT32((BASE_AIC+AIC_EOICR), ipr);
}

void
hal_interrupt_configure(int vector, int level, int up)
{
    CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
               vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
}

void hal_interrupt_set_level(int vector, int level)
{
    CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
               vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
}


//-----------------------------------------------------------------------------
// End of at91rm9200_misc.c