at91rm9200.h

ecos在9200上redboot实现

/*--------------------------------------------------------------------------*/

#define PID00   ((unsigned int) 0x01 <<  0)   /* FIQ  */
#define PID01   ((unsigned int) 0x01 <<  1)   /* SYS  */
#define PID02   ((unsigned int) 0x01 <<  2)   /* PIOA */
#define PID03   ((unsigned int) 0x01 <<  3)   /* PIOB */
#define PID04   ((unsigned int) 0x01 <<  4)   /* PIOC */
#define PID05   ((unsigned int) 0x01 <<  5)   /* PIOD */
#define PID06   ((unsigned int) 0x01 <<  6)   /* US0  */
#define PID07   ((unsigned int) 0x01 <<  7)   /* US1  */
#define PID08   ((unsigned int) 0x01 <<  8)   /* US2  */
#define PID09   ((unsigned int) 0x01 <<  9)   /* US3  */
#define PID10   ((unsigned int) 0x01 << 10)   /* MCI  */
#define PID11   ((unsigned int) 0x01 << 11)   /* UDP  */
#define PID12   ((unsigned int) 0x01 << 12)   /* TWI  */
#define PID13   ((unsigned int) 0x01 << 13)   /* SPI  */
#define PID14   ((unsigned int) 0x01 << 14)   /* SSC0 */
#define PID15   ((unsigned int) 0x01 << 15)   /* SSC1 */
#define PID16   ((unsigned int) 0x01 << 16)   /* SSC2 */
#define PID17   ((unsigned int) 0x01 << 17)   /* TC0  */
#define PID18   ((unsigned int) 0x01 << 18)   /* TC1  */
#define PID19   ((unsigned int) 0x01 << 19)   /* TC2  */
#define PID20   ((unsigned int) 0x01 << 20)   /* TC3  */
#define PID21   ((unsigned int) 0x01 << 21)   /* TC4  */
#define PID22   ((unsigned int) 0x01 << 22)   /* TC5  */
#define PID23   ((unsigned int) 0x01 << 23)   /* UHP  */
#define PID24   ((unsigned int) 0x01 << 24)   /* EMAC */
#define PID25   ((unsigned int) 0x01 << 25)   /* IRQ0 */
#define PID26   ((unsigned int) 0x01 << 26)   /* IRQ1 */
#define PID27   ((unsigned int) 0x01 << 27)   /* IRQ2 */
#define PID28   ((unsigned int) 0x01 << 28)   /* IRQ3 */
#define PID29   ((unsigned int) 0x01 << 29)   /* IRQ4 */
#define PID30   ((unsigned int) 0x01 << 30)   /* IRQ5 */
#define PID31   ((unsigned int) 0x01 << 31)   /* IRQ6 */


/*
**  Base of EMAC Address and offset of each register.
*/
#define BASE_EMAC   (0xFFFBC000)
#define EMAC_CTL    (0x00)  /* Network Control Register */
#define EMAC_CFG    (0x04)  /* Network Configuration Register */
#define EMAC_SR     (0x08)  /* Network Status Register */
#define EMAC_TAR    (0x0C)  /* Transmit Address Register */
#define EMAC_TCR    (0x10)  /* Transmit Control Register */
#define EMAC_TSR    (0x14)  /* Transmit Status Register */
#define EMAC_RBQP   (0x18)  /* Receive Buffer Queue Pointer */
#define EMAC_RSR    (0x20)  /* Receive Status Register */
#define EMAC_ISR    (0x24)  /* Interrupt Status Register */
#define EMAC_IER    (0x28)  /* Interrupt Enable Register */
#define EMAC_IDR    (0x2C)  /* Interrupt Disable Register */
#define EMAC_MAN    (0x34)  /* PHY Maintenance Register */
#define EMAC_SA1L   (0x98)  /* Specific Address 1 Low, First 4 bytes */
#define EMAC_SA1H   (0x9C)  /* Specific Address 1 High, Last 2 bytes */
#define EMAC_SA2L   (0xA0)  /* Specific Address 2 Low, First 4 bytes */
#define EMAC_SA2H   (0xA4)  /* Specific Address 2 High, Last 2 bytes */
/* EMAC_CTL */
#define C_EMAC_RE   ((unsigned int) 0x1 <<  2) // (EMAC) Receive enable.
#define C_EMAC_TE   ((unsigned int) 0x1 <<  3) // (EMAC) Transmit enable.
#define C_EMAC_MPE  ((unsigned int) 0x1 <<  4)  // Management Port Enable
#define C_EMAC_CSR  ((unsigned int) 0x1 <<  5)  // (EMAC) Clear statistics registers.
/* EMAC_CFG */
#define C_EMAC_SPD        ((unsigned int) 0x1 <<  0) // (EMAC) Speed.
#define C_EMAC_FD         ((unsigned int) 0x1 <<  1) // (EMAC) Full duplex.
#define C_EMAC_BR         ((unsigned int) 0x1 <<  2) // (EMAC) Bit rate.
#define C_EMAC_CAF        ((unsigned int) 0x1 <<  4) // (EMAC) Copy all frames.
#define C_EMAC_NBC        ((unsigned int) 0x1 <<  5) // (EMAC) No broadcast.
#define C_EMAC_MTI        ((unsigned int) 0x1 <<  6) // (EMAC) Multicast hash enable
#define C_EMAC_UNI        ((unsigned int) 0x1 <<  7) // (EMAC) Unicast hash enable.
#define C_EMAC_BIG        ((unsigned int) 0x1 <<  8) // (EMAC) Receive 1522 bytes.
#define C_EMAC_EAE        ((unsigned int) 0x1 <<  9) // (EMAC) External address match enable.
#define C_EMAC_CLK        ((unsigned int) 0x3 << 10) // (EMAC)
#define 	C_EMAC_CLK_HCLK_8               ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
#define 	C_EMAC_CLK_HCLK_16              ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
#define 	C_EMAC_CLK_HCLK_32              ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
#define 	C_EMAC_CLK_HCLK_64              ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
#define C_EMAC_RTY        ((unsigned int) 0x1 << 12) // (EMAC)
#define C_EMAC_RMII       ((unsigned int) 0x1 << 13) // (EMAC)
/* EMAC_SR */
#define C_EMAC_MDIO ((unsigned int) 0x1 <<  1)  // MDIO pin is set or not
#define C_EMAC_IDLE ((unsigned int) 0x1 <<  2)  // PHY logic is idle (0) or running (1).
/* EMAC_TSR */
#define C_EMAC_BNQ  ((unsigned int) 0x1 <<  4) // Ethernet transmit buffer not queued.
#define C_EMAC_COMP ((unsigned int) 0x1 <<  5) // Transmit complete. Set when a frame has been transmitted. Cleared by writing a one to this bit.
/* EMAC_ISR, EMAC_IER, EMAC_IDR */
#define C_EMAC_DONE   ((unsigned int) 0x1 <<  0) // (EMAC)
#define C_EMAC_RCOM   ((unsigned int) 0x1 <<  1) // (EMAC)
#define C_EMAC_RBNA   ((unsigned int) 0x1 <<  2) // (EMAC)
#define C_EMAC_TOVR   ((unsigned int) 0x1 <<  3) // (EMAC)
#define C_EMAC_TUND   ((unsigned int) 0x1 <<  4) // (EMAC)
#define C_EMAC_RTRY   ((unsigned int) 0x1 <<  5) // (EMAC)
#define C_EMAC_TBRE   ((unsigned int) 0x1 <<  6) // (EMAC)
#define C_EMAC_TCOM   ((unsigned int) 0x1 <<  7) // (EMAC)
#define C_EMAC_TIDLE  ((unsigned int) 0x1 <<  8) // (EMAC)
#define C_EMAC_LINK   ((unsigned int) 0x1 <<  9) // (EMAC)
#define C_EMAC_ROVR   ((unsigned int) 0x1 << 10) // (EMAC)
#define C_EMAC_HRESP  ((unsigned int) 0x1 << 11) // (EMAC)
/* EMAC_RSR */
#define C_EMAC_BNA    ((unsigned int) 0x1 <<  0) // Buffer not available.
#define C_EMAC_REC    ((unsigned int) 0x1 <<  1) // Frame received.
#define C_EMAC_OVR    ((unsigned int) 0x1 <<  2) // Ethernet transmit buffer overrun.
/* EMAC_MAN */
#define C_EMAC_DATA ((unsigned int) 0xFFFF <<  0)
#define C_EMAC_CODE ((unsigned int) 0x3 << 16)  // Must be written to 10 in accordance with IEEE standard 802.3.
#define C_EMAC_CODE_802_3 ((unsigned int) 0x2 << 16)
#define C_EMAC_REGA ((unsigned int) 0x1F << 18)  // Register address.
#define C_EMAC_PHYA ((unsigned int) 0x1F << 23)  // PHY address.
#define C_EMAC_RW   ((unsigned int) 0x3 << 28)  // Read/Write Operation.
#define C_EMAC_RW_R   ((unsigned int) 0x2 << 28)  // 10 is read.
#define C_EMAC_RW_W   ((unsigned int) 0x1 << 28)  // 01 is write.
#define C_EMAC_HIGH ((unsigned int) 0x1 << 30)  //
#define C_EMAC_LOW  ((unsigned int) 0x1 << 31)  //

/*
**  System Timer Interface Peripheral
*/
#define BASE_ST     (0xFFFFFD00)
#define ST_CR       (0x00)  /* Control Register */
#define ST_PIMR     (0x04)  /* Period Interval Mode Register */
#define ST_WDMR     (0x08)  /* Watchdog Mode Register */
#define ST_RTMR     (0x0C)  /* Real-time Mode Register */
#define ST_SR       (0x10)  /* Status Register */
#define ST_IER      (0x14)  /* Interrupt Enable Register */
#define ST_IDR      (0x18)  /* Interrupt Disable Register */
#define ST_IMR      (0x1C)  /* Interrupt Mask Register */
#define ST_RTAR     (0x20)  /* Real-time Alarm Register */
#define ST_CRTR     (0x24)  /* Current Real-time Register */
/* ST_SR, ST_IER, ST_IDR, ST_IMR */
#define C_ST_PITS   ((unsigned int) 0x1 <<  0) // (ST) Period Interval Timer Interrupt
#define C_ST_WDOVF  ((unsigned int) 0x1 <<  1) // (ST) Watchdog Overflow
#define C_ST_RTTINC ((unsigned int) 0x1 <<  2) // (ST) Real-time Timer Increment
#define C_ST_ALMS   ((unsigned int) 0x1 <<  3) // (ST) Alarm Status




/*
**  Base of Advanced Interrupt Controller (AIC) and offset of each register.
*/
#define BASE_AIC    (0xFFFFF000)
#define AIC_IECR    (0x120)   /* Interrupt Enable Command Register  */
#define AIC_IDCR    (0x124)   /* Interrupt Disable Command Register */
#define AIC_ICCR    (0x128)   /* Interrupt Clear Command Register   */
#define AIC_EOICR   (0x130)   /* End of Interrupt Command Register  */



/*
** Base of Debug Unit (DBGU) and offset of each register.
*/
#define BASE_DBGU   (0xFFFFF200)
#define DBGU_CR     (0x0000)  /* Control Register             */
#define DBGU_MR     (0x0004)  /* Mode Register                */
#define DBGU_IER    (0x0008)  /* Interrupt Enable Register    */
#define DBGU_IDR    (0x000C)  /* Interrupt Disable Register   */
#define DBGU_IMR    (0x0010)  /* Interrupt Mask Register      */
#define DBGU_SR     (0x0014)  /* Status Register              */
#define DBGU_RHR    (0x0018)  /* Receive Holding Register     */
#define DBGU_THR    (0x001C)  /* Transmit Holding Register    */
#define DBGU_BRGR   (0x0020)  /* Baud Rate Generator Register */
/* ?? */
#define DBGU_TTGR   (0x0028)  /* Transmitter Time-guard Register */
#define DBGU_RPR    (0x100)   /* (PDC_RPR) Receive Pointer Register        */
#define DBGU_RCR    (0x104)   /* (PDC_RCR) Receive Counter Register        */
#define DBGU_TPR    (0x108)   /* (PDC_TPR) Transmit Pointer Register       */
#define DBGU_TCR    (0x10C)   /* (PDC_TCR) Transmit Counter Register       */
#define DBGU_RNPR   (0x110)   /* (PDC_RNPR) Receive Next Pointer Register  */
#define DBGU_RNCR   (0x114)   /* (PDC_RNCR) Receive Next Counter Register  */
#define DBGU_TNPR   (0x118)   /* (PDC_TNPR) Transmit Next Pointer Register */
#define DBGU_TNCR   (0x11C)   /* (PDC_TNCR) Transmit Next Counter Register */
#define DBGU_PTCR   (0x120)   /* (PDC_PTCR) PDC Transfer Control Register  */
#define DBGU_PTSR   (0x124)   /* (PDC_PTSR) PDC Transfer Status Register   */
/* DBGU_CR */
#define C_US_RSTRX  ((unsigned int) 0x1 << 2)   // Reset Receiver
#define C_US_RSTTX  ((unsigned int) 0x1 << 3)   // Reset Transmitter
#define C_US_RXEN   ((unsigned int) 0x1 << 4)   // Receiver Enable
#define C_US_RXDIS  ((unsigned int) 0x1 << 5)   // Receiver Disable
#define C_US_TXEN   ((unsigned int) 0x1 << 6)   // Transmitter Enable
#define C_US_TXDIS  ((unsigned int) 0x1 << 7)   // Transmitter Disable
#define C_US_RSTSTA ((unsigned int) 0x1 << 8)   // Reset Status Bits
/* DBGU_SR */
#define C_US_RXRDY  ((unsigned int) 0x1 << 0)   // Receiver Ready
#define C_US_TXRDY  ((unsigned int) 0x1 << 1)   // Transmitter Ready
/* DBGU_PTCR */
#define C_PDC_RXTEN   ((unsigned int) 0x1 << 0) // Receiver Transfer Enable
#define C_PDC_RXTDIS  ((unsigned int) 0x1 << 1) // Receiver Transfer Disable
#define C_PDC_TXTEN   ((unsigned int) 0x1 << 8) // Transmitter Transfer Enable
#define C_PDC_TXTDIS  ((unsigned int) 0x1 << 9) // Transmitter Transfer Disable


/*
**  Base of Parallel Input/Output Controller (PIO) and offset of each register.
*/
#define BASE_PIOA   (0xFFFFF400)
#define BASE_PIOB   (0xFFFFF600)
#define BASE_PIOC   (0xFFFFF800)
#define BASE_PIOD   (0xFFFFFA00)
#define PIO_PDR     (0x04)    /* PIO Disable Register */
#define PIO_ASR     (0x70)    /* Select A Register    */
#define PIO_BSR     (0x74)    /* Select B Register    */

#define C_PIO_PA07  ((unsigned int) 1 <<  7)    // Pin Controlled by PA07
#define C_PA7_ETXCK_EREFCK ((unsigned int) C_PIO_PA7) //  Ethernet MAC Transmit Clock/Reference Clock
#define C_PA7_PCK2    ((unsigned int)  C_PIO_PA7) //  PMC Programmable Clock 2
#define C_PIO_PA08  ((unsigned int) 1 <<  8)    // Pin Controlled by PA08
#define C_PA8_ETXEN   ((unsigned int) C_PIO_PA8) //  Ethernet MAC Transmit Enable
#define C_PA8_MCCDB   ((unsigned int) C_PIO_PA8) //  Multimedia Card B Command
#define C_PIO_PA09  ((unsigned int) 1 <<  9)    // Pin Controlled by PA09
#define C_PA9_ETX0    ((unsigned int) C_PIO_PA9) //  Ethernet MAC Transmit Data 0
#define C_PA9_MCDB0   ((unsigned int) C_PIO_PA9) //  Multimedia Card B Data 0
#define C_PIO_PA10  ((unsigned int) 1 << 10)    // Pin Controlled by PA10
#define C_PA10_ETX1   ((unsigned int) C_PIO_PA10) //  Ethernet MAC Transmit Data 1
#define C_PA10_MCDB1  ((unsigned int) C_PIO_PA10) //  Multimedia Card B Data 1
#define C_PIO_PA11  ((unsigned int) 1 << 11)    // Pin Controlled by PA11
#define C_PA11_ECRS_ECRSDV ((unsigned int) C_PIO_PA11) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
#define C_PA11_MCDB2  ((unsigned int) C_PIO_PA11) //  Multimedia Card B Data 2
#define C_PIO_PA12  ((unsigned int) 1 << 12)    // Pin Controlled by PA12
#define C_PA12_ERX0   ((unsigned int) C_PIO_PA12) //  Ethernet MAC Receive Data 0
#define C_PA12_MCDB3  ((unsigned int) C_PIO_PA12) //  Multimedia Card B Data 3
#define C_PIO_PA13  ((unsigned int) 1 << 13)    // Pin Controlled by PA13
#define C_PA13_ERX1   ((unsigned int) C_PIO_PA13) //  Ethernet MAC Receive Data 1
#define C_PA13_TCLK0  ((unsigned int) C_PIO_PA13) //  Timer Counter 0 external clock input
#define C_PIO_PA14  ((unsigned int) 1 << 14)    // Pin Controlled by PA14
#define C_PA14_ERXER  ((unsigned int) C_PIO_PA14) //  Ethernet MAC Receive Error
#define C_PA14_TCLK1  ((unsigned int) C_PIO_PA14) //  Timer Counter 1 external clock input
#define C_PIO_PA15  ((unsigned int) 1 << 15)    // Pin Controlled by PA15
#define C_PA15_EMDC   ((unsigned int) C_PIO_PA15) //  Ethernet MAC Management Data Clock
#define C_PA15_TCLK2  ((unsigned int) C_PIO_PA15) //  Timer Counter 2 external clock input
#define C_PIO_PA16  ((unsigned int) 1 << 16)    // Pin Controlled by PA16
#define C_PA16_EMDIO  ((unsigned int) C_PIO_PA16) //  Ethernet MAC Management Data Input/Output
#define C_PA16_IRQ6   ((unsigned int) C_PIO_PA16) //  AIC Interrupt input 6

#define C_PIO_PA30  ((unsigned int) 1 << 30)    // Pin Controlled by PA30
#define C_PA30_DRXD   ((unsigned int) C_PIO_PA30) //  DBGU Debug Receive Data
#define C_PA30_CTS2   (unsigned int) C_PIO_PA30) //  Usart 2 Clear To Send
#define C_PIO_PA31  ((unsigned int) 1 << 31)    // Pin Controlled by PA31
#define C_PA31_DTXD   ((unsigned int) C_PIO_PA31) //  DBGU Debug Transmit Data
#define C_PA31_RTS2   (unsigned int) C_PIO_PA31)  //  USART 2 Ready To Send


/*
**  Power Management Controler (PMC) and offset of each register.
*/
#define BASE_PMC        (0xFFFFFC00)
#define PMC_PCER        (0x10)  /* Peripheral Clock Enable Register */
#define PMC_CKGR_MOR    (0x20)  /* Main Oscillator Register       */
#define PMC_CKGR_MCFR   (0x24)  /* Main Clock Frequency Register  */
#define PMC_CKGR_PLLAR  (0x28)  /* PLL A Register                 */
#define PMC_CKGR_PLLBR  (0x2C)  /* PLL B Register                 */
#define PMC_MCKR        (0x30)  /* Master Clock Register          */
#define PMC_IER         (0x60)  /* Interrupt Enable Register      */
#define PMC_IDR         (0x64)  /* Interrupt Disable Register     */
#define PMC_SR          (0x68)  /* Status Register                */
/* PMC_IER, PMC_SR, PMC_SR */
#define C_PMC_LOCKA ((unsigned int) 0x1 <<  1)  // (PMC) PLL A Status/Enable/Disable/Mask


#endif // CYGONCE_AT91RM9200_H
//-----------------------------------------------------------------------------
// end of at91rm9200.h