📄 hal_platform_ints.h
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#ifndef CYGONCE_HAL_PLATFORM_INTS_H#define CYGONCE_HAL_PLATFORM_INTS_H//==========================================================================//// hal_platform_ints.h//// HAL Interrupt and clock support////==========================================================================//####ECOSGPLCOPYRIGHTBEGIN####// -------------------------------------------// This file is part of eCos, the Embedded Configurable Operating System.// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.//// eCos is free software; you can redistribute it and/or modify it under// the terms of the GNU General Public License as published by the Free// Software Foundation; either version 2 or (at your option) any later version.//// eCos is distributed in the hope that it will be useful, but WITHOUT ANY// WARRANTY; without even the implied warranty of MERCHANTABILITY or// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License// for more details.//// You should have received a copy of the GNU General Public License along// with eCos; if not, write to the Free Software Foundation, Inc.,// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.//// As a special exception, if other files instantiate templates or use macros// or inline functions from this file, or you compile this file and link it// with other works to produce a work based on this file, this file does not// by itself cause the resulting work to be covered by the GNU General Public// License. However the source code for this file must still be made available// in accordance with section (3) of the GNU General Public License.//// This exception does not invalidate any other reasons why a work based on// this file might be covered by the GNU General Public License.//// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.// at http://sources.redhat.com/ecos/ecos-license/// -------------------------------------------//####ECOSGPLCOPYRIGHTEND####//==========================================================================//#####DESCRIPTIONBEGIN####//// Author(s): Jiun-Shian H. <asky@syncom.com.tw>// Contributors: Jiun-Shian H. <asky@syncom.com.tw>// Date: 2005-08-10// Purpose: Define Interrupt support// Description: The interrupt details for the Atmel AT91RM9200 are defined here.// Usage:// #include <cyg/hal/hal_platform_ints.h>// ...//////####DESCRIPTIONEND####////==========================================================================#include <cyg/hal/at91rm9200.h>// These are interrupts on the AT91RM9200/*--------------------------------------------------------------------------*/#define CYGNUM_HAL_INTERRUPT_EINT0 0#define CYGNUM_HAL_INTERRUPT_EINT1 1#define CYGNUM_HAL_INTERRUPT_EINT2 2#define CYGNUM_HAL_INTERRUPT_EINT3 3#define CYGNUM_HAL_INTERRUPT_EINT4_7 4#define CYGNUM_HAL_INTERRUPT_EINT8_23 5#define CYGNUM_HAL_INTERRUPT_NOTUSED6 6#define CYGNUM_HAL_INTERRUPT_BAT_FLT 7#define CYGNUM_HAL_INTERRUPT_TICK 8#define CYGNUM_HAL_INTERRUPT_WDT 9#define CYGNUM_HAL_INTERRUPT_TIMER0 10#define CYGNUM_HAL_INTERRUPT_TIMER1 11#define CYGNUM_HAL_INTERRUPT_TIMER2 12#define CYGNUM_HAL_INTERRUPT_TIMER3 13#define CYGNUM_HAL_INTERRUPT_TIMER4 14#define CYGNUM_HAL_INTERRUPT_UART2 15#define CYGNUM_HAL_INTERRUPT_LCD 16#define CYGNUM_HAL_INTERRUPT_DMA0 17#define CYGNUM_HAL_INTERRUPT_DMA1 18#define CYGNUM_HAL_INTERRUPT_DMA2 19#define CYGNUM_HAL_INTERRUPT_DMA3 20#define CYGNUM_HAL_INTERRUPT_SDI 21#define CYGNUM_HAL_INTERRUPT_SPI0 22#define CYGNUM_HAL_INTERRUPT_UART1 23#define CYGNUM_HAL_INTERRUPT_NOTUSED24 24#define CYGNUM_HAL_INTERRUPT_USBD 25#define CYGNUM_HAL_INTERRUPT_USBH 26#define CYGNUM_HAL_INTERRUPT_IIC 27#define CYGNUM_HAL_INTERRUPT_UART0 28#define CYGNUM_HAL_INTERRUPT_SPI1 29#define CYGNUM_HAL_INTERRUPT_RTCC 30#define CYGNUM_HAL_INTERRUPT_ADC 31/*--------------------------------------------------------------------------*//* cf. Table 4-8. Peripheral Identifiers */#define CYGNUM_HAL_INTERRUPT_PID00 (0)#define CYGNUM_HAL_INTERRUPT_PID01 (1)#define CYGNUM_HAL_INTERRUPT_PID02 (2)#define CYGNUM_HAL_INTERRUPT_PID03 (3)#define CYGNUM_HAL_INTERRUPT_PID04 (4)#define CYGNUM_HAL_INTERRUPT_PID05 (5)#define CYGNUM_HAL_INTERRUPT_PID06 (6)#define CYGNUM_HAL_INTERRUPT_PID07 (7)#define CYGNUM_HAL_INTERRUPT_PID08 (8)#define CYGNUM_HAL_INTERRUPT_PID09 (9)#define CYGNUM_HAL_INTERRUPT_PID10 (10)#define CYGNUM_HAL_INTERRUPT_PID11 (11)#define CYGNUM_HAL_INTERRUPT_PID12 (12)#define CYGNUM_HAL_INTERRUPT_PID13 (13)#define CYGNUM_HAL_INTERRUPT_PID14 (14)#define CYGNUM_HAL_INTERRUPT_PID15 (15)#define CYGNUM_HAL_INTERRUPT_PID16 (16)#define CYGNUM_HAL_INTERRUPT_PID17 (17)#define CYGNUM_HAL_INTERRUPT_PID18 (18)#define CYGNUM_HAL_INTERRUPT_PID19 (19)#define CYGNUM_HAL_INTERRUPT_PID20 (20)#define CYGNUM_HAL_INTERRUPT_PID21 (21)#define CYGNUM_HAL_INTERRUPT_PID22 (22)#define CYGNUM_HAL_INTERRUPT_PID23 (23)#define CYGNUM_HAL_INTERRUPT_PID24 (24)#define CYGNUM_HAL_INTERRUPT_PID25 (25)#define CYGNUM_HAL_INTERRUPT_PID26 (26)#define CYGNUM_HAL_INTERRUPT_PID27 (27)#define CYGNUM_HAL_INTERRUPT_PID28 (28)#define CYGNUM_HAL_INTERRUPT_PID29 (29)#define CYGNUM_HAL_INTERRUPT_PID30 (30)#define CYGNUM_HAL_INTERRUPT_PID31 (31)#define CYGNUM_HAL_INTERRUPT_FIQ (CYGNUM_HAL_INTERRUPT_PID00)/* System Interrupt, e.g. DBG, RTC */#define CYGNUM_HAL_INTERRUPT_SYS (CYGNUM_HAL_INTERRUPT_PID01)#define CYGNUM_HAL_INTERRUPT_PIOA (CYGNUM_HAL_INTERRUPT_PID02)#define CYGNUM_HAL_INTERRUPT_PIOB (CYGNUM_HAL_INTERRUPT_PID03)#define CYGNUM_HAL_INTERRUPT_PIOC (CYGNUM_HAL_INTERRUPT_PID04)#define CYGNUM_HAL_INTERRUPT_PIOD (CYGNUM_HAL_INTERRUPT_PID05)#define CYGNUM_HAL_INTERRUPT_US0 (CYGNUM_HAL_INTERRUPT_PID06)#define CYGNUM_HAL_INTERRUPT_US1 (CYGNUM_HAL_INTERRUPT_PID07)#define CYGNUM_HAL_INTERRUPT_US2 (CYGNUM_HAL_INTERRUPT_PID08)#define CYGNUM_HAL_INTERRUPT_US3 (CYGNUM_HAL_INTERRUPT_PID09)#define CYGNUM_HAL_INTERRUPT_MCI (CYGNUM_HAL_INTERRUPT_PID10)#define CYGNUM_HAL_INTERRUPT_UDP (CYGNUM_HAL_INTERRUPT_PID11)#define CYGNUM_HAL_INTERRUPT_TWI (CYGNUM_HAL_INTERRUPT_PID12)#define CYGNUM_HAL_INTERRUPT_SPI (CYGNUM_HAL_INTERRUPT_PID13)#define CYGNUM_HAL_INTERRUPT_SSC0 (CYGNUM_HAL_INTERRUPT_PID14)#define CYGNUM_HAL_INTERRUPT_SSC1 (CYGNUM_HAL_INTERRUPT_PID15)#define CYGNUM_HAL_INTERRUPT_SSC2 (CYGNUM_HAL_INTERRUPT_PID16)#define CYGNUM_HAL_INTERRUPT_TC0 (CYGNUM_HAL_INTERRUPT_PID17)#define CYGNUM_HAL_INTERRUPT_TC1 (CYGNUM_HAL_INTERRUPT_PID18)#define CYGNUM_HAL_INTERRUPT_TC2 (CYGNUM_HAL_INTERRUPT_PID19)#define CYGNUM_HAL_INTERRUPT_TC3 (CYGNUM_HAL_INTERRUPT_PID20)#define CYGNUM_HAL_INTERRUPT_TC4 (CYGNUM_HAL_INTERRUPT_PID21)#define CYGNUM_HAL_INTERRUPT_TC5 (CYGNUM_HAL_INTERRUPT_PID22)#define CYGNUM_HAL_INTERRUPT_UHP (CYGNUM_HAL_INTERRUPT_PID23)#define CYGNUM_HAL_INTERRUPT_EMAC (CYGNUM_HAL_INTERRUPT_PID24)#define CYGNUM_HAL_INTERRUPT_IRQ0 (CYGNUM_HAL_INTERRUPT_PID25)#define CYGNUM_HAL_INTERRUPT_IRQ1 (CYGNUM_HAL_INTERRUPT_PID26)#define CYGNUM_HAL_INTERRUPT_IRQ2 (CYGNUM_HAL_INTERRUPT_PID27)#define CYGNUM_HAL_INTERRUPT_IRQ3 (CYGNUM_HAL_INTERRUPT_PID28)#define CYGNUM_HAL_INTERRUPT_IRQ4 (CYGNUM_HAL_INTERRUPT_PID29)#define CYGNUM_HAL_INTERRUPT_IRQ5 (CYGNUM_HAL_INTERRUPT_PID30)#define CYGNUM_HAL_INTERRUPT_IRQ6 (CYGNUM_HAL_INTERRUPT_PID31)#define CYGNUM_HAL_INTERRUPT_NONE -1#define CYGNUM_HAL_ISR_MIN 0#define CYGNUM_HAL_ISR_MAX (CYGNUM_HAL_INTERRUPT_PID31)#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX - CYGNUM_HAL_ISR_MIN + 1)// The vector used by the Real time clock#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER4//----------------------------------------------------------------------------// Reset.// Watchdog is started with a very small delay to Reset immediatly.#if 0#define HAL_PLATFORM_RESET() \do { \ HAL_WRITE_UINT32(WTCON, 0); \ HAL_WRITE_UINT32(WTDAT, 1); \ HAL_WRITE_UINT32(WTCON, (1<<0)|(0<<2)|(0<<3)|(1<<5)|(0<<8)); \} while(0)#else#define HAL_PLATFORM_RESET() {;}#endif /* 0/1 */#if 0// Base of flash#define HAL_PLATFORM_RESET_ENTRY 0x00000000#else// entry of eCos (Base of SDRAM)#define HAL_PLATFORM_RESET_ENTRY (0x20000040u)#endif /* 0/1 */#endif // CYGONCE_HAL_PLATFORM_INTS_H⌨️ 快捷键说明
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