fifo_1.v

这是一个先进先出FIFO存储器的设计源码

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    08:50:44 12/28/2007 
// Design Name: 
// Module Name:    fifo_1 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module fifo_1(clk, rst, write, read, data_in, data_out, rdinc, wrinc);
input clk;
input rst;
input write;
input read;
input [7:0] data_in;

output [7:0] data_out;
output [3:0] rdinc;
output [3:0] wrinc;

reg  [7:0]data_out;
reg [3:0] rdinc;
reg [3:0]wrinc;

reg full,empty,s,s1;
reg [7:0]data_reg [9:0];
always@(posedge clk)
begin
if(rst) begin rdinc=0;wrinc=0;empty=1;full=0;s=0;s1=0; end
else begin 
if(read && !empty) 
begin
if((wrinc[3:0]==rdinc[3:0]) && !(s ^ s1)) begin empty=1;end
       else begin data_out=data_reg[rdinc[3:0]];
                  full=0; 
                  if(rdinc==9) begin rdinc=0;s=~s;end 
                          else begin rdinc=rdinc+1;end  
            end
end
else if(write && !full)
begin 
if((wrinc[3:0]==rdinc[3:0 ]) && (s ^ s1)) begin full=1;end
       else  begin data_reg[wrinc[3:0]]=data_in;
                   empty=0;
                   if(wrinc==9) begin wrinc=0;s1=~s1;end 
                           else begin wrinc=wrinc+1;end   
             end
end
end
end

endmodule