pentium.txt

BIOS中断大全！ 英文文档

E2       cb  LOOP rel8               Dec count;jump if count # 0
E1       cb  LOOPE rel8              Dec count;jump if count # 0 and ZF=1
E1       cb  LOOPZ rel8              Dec count;jump if count # 0 and ZF=1
E0       cb  LOOPNE rel8             Dec count;jump if count # 0 and ZF=0
E0       cb  LOOPNZ rel8             Dec count;jump if count # 0 and ZF=0
0F 03 /r     LSL r16,r/m16           Load Segment Limit
0F 03 /r     LSL r32,r/m32           Load Segment Limit
0F B2 /r     LSS r32,m16:32          Load SS:r32 with far ptr
0F 00 /3     LTR r/m16               Load Task Register
88    /r     MOV r/m8,r8             Move 
89    /r     MOV r/m32,r32           Move 
8A    /r     MOV r8,r/m8             Move 
8B    /r     MOV r32,r/m32           Move 
8C    /r     MOV r/m16,Sreg**        Move segment register to r/m16
8E    /r     MOV Sreg,r/m16**        Move r/m16 to segment register
A0           MOV AL, moffs8*         Move byte at ( seg:offset) to AL
A1           MOV AX, moffs16*        Move word at ( seg:offset) to AX
A1           MOV EAX, moffs32*       Move dword at ( seg:offset) to EAX
A2           MOV moffs8*,AL          Move AL to ( seg:offset)
A3           MOV moffs16*,AX         Move AX to ( seg:offset)
A3           MOV moffs32*,EAX        Move EAX to ( seg:offset)
B0+rb        MOV r8,imm8             Move imm8 to r8
B8+rd        MOV r32,imm32           Move imm32 to r32
C6    /0 ib  MOV r/m8,imm8           Move imm8 to r/m8
C7    /0 id  MOV r/m32,imm32         Move imm32 to r/m32
0F 22 /r     MOV CR0, r32            Move r32 to CR0
0F 22 /r     MOV CR2, r32            Move r32 to CR2
0F 22 /r     MOV CR3, r32            Move r32 to CR3
0F 22 /r     MOV CR4, r32            Move r32 to CR4
0F 20 /r     MOV r32,CR0             Move CR0 to r32
0F 20 /r     MOV r32,CR2             Move CR2 to r32
0F 20 /r     MOV r32,CR3             Move CR3 to r32
0F 20 /r     MOV r32,CR4             Move CR4 to r32
0F 21 /r     MOV r32,DR0-DR7         Move debug register to r32
0F 23 /r     MOV DR0-DR7,r32         Move r32 to debug register
0F 6E /r     MOVD mm,r/m32           Move doubleword from r/m32 to mm
0F 7E /r     MOVD r/m32,mm           Move doubleword from mm to r/m32
0F 6F /r     MOVQ mm,mm/m64          Move quadword from mm/m64 to mm
0F 7F /r     MOVQ mm/m64,mm          Move quadword from mm to mm/m64
A4           MOVS m8,m8              Move byte at DS:(E)SI to  ES:(E)DI
A5           MOVS m32,m32            Move dword at DS:(E)SI to  ES:(E)DI
0F BE /r     MOVSX r32,r/m8          Move byte to doubleword, sign-extension
0F BF /r     MOVSX r32,r/m16         Move word to doubleword, sign-extension
0F B6 /r     MOVZX r32,r/m8          Move byte to doubleword, zero-extension
0F B7 /r     MOVZX r32,r/m16         Move word to doubleword, zero-extension
F6    /4     MUL r/m8                Unsigned multiply 
F7    /4     MUL r/m32               Unsigned multiply 
F6    /3     NEG r/m8                Two's complement negate r/m8
F7    /3     NEG r/m32               Two's complement negate r/m32
90           NOP                     No operation
F6    /2     NOT r/m8                Reverse each bit of r/m8
F7    /2     NOT r/m32               Reverse each bit of r/m32
0C       ib  OR AL,imm8              OR
0D       id  OR EAX,imm32            OR 
80    /1 ib  OR r/m8,imm8            OR 
81    /1 id  OR r/m32,imm32          OR 
83    /1 ib  OR r/m32,imm8           OR 
08    /r     OR r/m8,r8              OR 
09    /r     OR r/m32,r32            OR 
0A    /r     OR r8,r/m8              OR 
0B    /r     OR r32,r/m32            OR 
E6       ib  OUT imm8,AL             Output byte in AL to I/O(imm8)
E7       ib  OUT imm8,EAX            Output dword in EAX to I/O(imm8)
EE           OUT DX,AL               Output byte in AL to I/O(DX)
EF           OUT DX,EAX              Output dword in EAX to I/O(DX)
6E           OUTS DX,m8              Output byte from DS:(E)SI to I/O(DX)
6F           OUTS DX,m32             Output dword from DS:(E)SI to I/O (DX)
0F 63 /r     PACKSSWB mm,mm/m64      Pack with Signed Saturation
0F 6B /r     PACKSSDW mm,mm/m64      Pack with Signed Saturation
0F 67 /r     PACKUSWB mm,mm/m64      Pack with Unsigned Saturation
0F FC /r     PADDB mm,mm/m64         Add packed bytes 
0F FD /r     PADDW mm,mm/m64         Add packed words 
0F FE /r     PADDD mm,mm/m64         Add packed dwords 
0F EC /r     PADDSB mm,mm/m64        Add signed packed bytes 
0F ED /r     PADDSW mm,mm/m64        Add signed packed words 
0F DC /r     PADDUSB mm,mm/m64       Add unsigned pkd bytes 
0F DD /r     PADDUSW mm,mm/m64       Add unsigned pkd words 
0F DB /r     PAND mm,mm/m64          AND quadword from .. to ..
0F DF /r     PANDN mm,mm/m64         And qword from .. to NOT qw in mm
0F 74 /r     PCMPEQB mm,mm/m64       Packed Compare for Equal
0F 75 /r     PCMPEQW mm,mm/m64       Packed Compare for Equal
0F 76 /r     PCMPEQD mm,mm/m64       Packed Compare for Equal
0F 64 /r     PCMPGTB mm,mm/m64       Packed Compare for GT
0F 65 /r     PCMPGTW mm,mm/m64       Packed Compare for GT
0F 66 /r     PCMPGTD mm,mm/m64       Packed Compare for GT
0F F5 /r     PMADDWD mm,mm/m64       Packed Multiply and Add
0F E5 /r     PMULHW mm,mm/m64        Packed Multiply High
0F D5 /r     PMULLW mm,mm/m64        Packed Multiply Low
8F    /0     POP m32                 Pop m32
58+rd        POP r32                 Pop r32
1F           POP DS                  Pop DS
07           POP ES                  Pop ES
17           POP SS                  Pop SS
0F A1        POP FS                  Pop FS
0F A9        POP GS                  Pop GS
61           POPAD                   Pop EDI,... and EAX
9D           POPFD                   Pop Stack into EFLAGS Register
0F EB /r     POR mm,mm/m64           OR qword from .. to mm
0F F1 /r     PSLLW mm,mm/m64         Packed Shift Left Logical
0F 71 /6 ib  PSLLW mm,imm8           Packed Shift Left Logical
0F F2 /r     PSLLD mm,mm/m64         Packed Shift Left Logical
0F 72 /6 ib  PSLLD mm,imm8           Packed Shift Left Logical
0F F3 /r     PSLLQ mm,mm/m64         Packed Shift Left Logical
0F 73 /6 ib  PSLLQ mm,imm8           Packed Shift Left Logical
0F E1 /r     PSRAW mm,mm/m64         Packed Shift Right Arithmetic
0F 71 /4 ib  PSRAW mm,imm8           Packed Shift Right Arithmetic
0F E2 /r     PSRAD mm,mm/m64         Packed Shift Right Arithmetic
0F 72 /4 ib  PSRAD mm,imm8           Packed Shift Right Arithmetic
0F D1 /r     PSRLW mm,mm/m64         Packed Shift Right Logical 
0F 71 /2 ib  PSRLW mm,imm8           Packed Shift Right Logical 
0F D2 /r     PSRLD mm,mm/m64         Packed Shift Right Logical 
0F 72 /2 ib  PSRLD mm,imm8           Packed Shift Right Logical 
0F D3 /r     PSRLQ mm,mm/m64         Packed Shift Right Logical 
0F 73 /2 ib  PSRLQ mm,imm8           Packed Shift Right Logical 
0F F8 /r     PSUBB mm,mm/m64         Packed Subtract
0F F9 /r     PSUBW mm,mm/m64         Packed Subtract
0F FA /r     PSUBD mm,mm/m64         Packed Subtract
0F E8 /r     PSUBSB mm,mm/m64        Packed Subtract with Saturation
0F E9 /r     PSUBSW mm,mm/m64        Packed Subtract with Saturation
0F D8 /r     PSUBUSB mm,mm/m64       Packed Subtract Unsigned with S.
0F D9 /r     PSUBUSW mm,mm/m64       Packed Subtract Unsigned with S.
0F 68 /r     PUNPCKHBW mm,mm/m64     Unpack High Packed Data
0F 69 /r     PUNPCKHWD mm,mm/m64     Unpack High Packed Data
0F 6A /r     PUNPCKHDQ mm,mm/m64     Unpack High Packed Data
0F 60 /r     PUNPCKLBW mm,mm/m64     Unpack Low Packed Data
0F 61 /r     PUNPCKLWD mm,mm/m64     Unpack Low Packed Data
0F 62 /r     PUNPCKLDQ mm,mm/m64     Unpack Low Packed Data
FF    /6     PUSH r/m32              Push r/m32
50+rd        PUSH r32                Push r32
6A       ib  PUSH imm8               Push imm8
68       id  PUSH imm32              Push imm32
0E           PUSH CS                 Push CS
16           PUSH SS                 Push SS
1E           PUSH DS                 Push DS
06           PUSH ES                 Push ES
0F A0        PUSH FS                 Push FS
0F A8        PUSH GS                 Push GS
60           PUSHAD                  Push All g-regs
9C           PUSHFD                  Push EFLAGS
0F EF /r     PXOR mm,mm/m64          XOR qword
D0    /2     RCL r/m8,1              Rotate 9 bits left once
D2    /2     RCL r/m8,CL             Rotate 9 bits left CL times
C0    /2 ib  RCL r/m8,imm8           Rotate 9 bits left imm8 times
D1    /2     RCL r/m32,1             Rotate 33 bits left once
D3    /2     RCL r/m32,CL            Rotate 33 bits left CL times
C1    /2 ib  RCL r/m32,imm8          Rotate 33 bits left imm8 times
D0    /3     RCR r/m8,1              Rotate 9 bits right once
D2    /3     RCR r/m8,CL             Rotate 9 bits right CL times
C0    /3 ib  RCR r/m8,imm8           Rotate 9 bits right imm8 times
D1    /3     RCR r/m32,1             Rotate 33 bits right once
D3    /3     RCR r/m32,CL            Rotate 33 bits right CL times
C1    /3 ib  RCR r/m32,imm8          Rotate 33 bits right imm8 times
D0    /0     ROL r/m8,1              Rotate 8 bits r/m8 left once
D2    /0     ROL r/m8,CL             Rotate 8 bits r/m8 left CL times
C0    /0 ib  ROL r/m8,imm8           Rotate 8 bits r/m8 left imm8 times
D1    /0     ROL r/m32,1             Rotate 32 bits r/m32 left once
D3    /0     ROL r/m32,CL            Rotate 32 bits r/m32 left CL times
C1    /0 ib  ROL r/m32,imm8          Rotate 32 bits r/m32 left imm8 times
D0    /1     ROR r/m8,1              Rotate 8 bits r/m8 right once
D2    /1     ROR r/m8,CL             Rotate 8 bits r/m8 right CL times
C0    /1 ib  ROR r/m8,imm8           Rotate 8 bits r/m16 right imm8 times
D1    /1     ROR r/m32,1             Rotate 32 bits r/m32 right once
D3    /1     ROR r/m32,CL            Rotate 32 bits r/m32 right CL times
C1    /1 ib  ROR r/m32,imm8          Rotate 32 bits r/m32 right imm8 times
0F 32        RDMSR                   Read from Model Specific Register
0F 33        RDPMC                   Read Performance-Monitoring counters
0F 31        RDTSC                   Read Time-Stamp Counter
F3 6C        REP INS m8,DX           Input ECX bytes from port DX into ES:[(E)DI]
F3 6D        REP INS m32,DX          Input ECX dwords from port DX into ES:[(E)DI]
F3 A4        REP MOVS m8,m8          Move ECX bytes from DS:[(E)SI] to ES:[(E)DI]
F3 A5        REP MOVS m32,m32        Move ECX dwords from DS:[(E)SI] to ES:[(E)DI]
F3 6E        REP OUTS DX,m8          Output ECX bytes from DS:[(E)SI] to port DX
F3 6F        REP OUTS DX,m32         Output ECX dwords from DS:[(E)SI] to port DX
F3 AC        REP LODS AL             Load ECX bytes from DS:[(E)SI] to AL
F3 AD        REP LODS EAX            Load ECX dwords from DS:[(E)SI] to EAX
F3 AA        REP STOS m8             Fill ECX bytes at ES:[(E)DI] with AL
F3 AB        REP STOS m32            Fill ECX dwords at ES:[(E)DI] with EAX
F3 A6        REPE CMPS m8,m8         Find nonmatching bytes in m and m
F3 A7        REPE CMPS m32,m32       Find nonmatching dwords in m and m
F3 AE        REPE SCAS m8            Find non-AL byte starting at 
F3 AF        REPE SCAS m32           Find non-EAX dword starting at 
F2 A6        REPNE CMPS m8,m8        Find matching bytes in m and m
F2 A7        REPNE CMPS m32,m32      Find matching dwords in m and m
F2 AE        REPNE SCAS m8           Find AL, starting at ES:[(E)DI]
F2 AF        REPNE SCAS m32          Find EAX, starting at ES:[(E)DI]
C3           RET                     Near return 
CB           RET                     Far return 
C2       iw  RET imm16               Near return, pop imm16 bytes from stack
CA       iw  RET imm16               Far return, pop imm16 bytes from stack
0F AA        RSM                     Resume from System Management
9E           SAHF                    Store AH into Flags
D0    /4     SAL r/m8,1              Shift Arithmetic Left
D2    /4     SAL r/m8,CL             Shift Arithmetic Left
C0    /4 ib  SAL r/m8,imm8           Shift Arithmetic Left
D1    /4     SAL r/m32,1             Shift Arithmetic Left
D3    /4     SAL r/m32,CL            Shift Arithmetic Left
C1    /4 ib  SAL r/m32,imm8          Shift Arithmetic Left
D0    /7     SAR r/m8,1              Shift Arithmetic Right
D2    /7     SAR r/m8,CL             Shift Arithmetic Right
C0    /7 ib  SAR r/m8,imm8           Shift Arithmetic Right
D1    /7     SAR r/m32,1             Shift Arithmetic Right
D3    /7     SAR r/m32,CL            Shift Arithmetic Right
C1    /7 ib  SAR r/m32,imm8          Shift Arithmetic Right
D0    /4     SHL r/m8,1              Shift Logical Left
D2    /4     SHL r/m8,CL             Shift Logical Left
C0    /4 ib  SHL r/m8,imm8           Shift Logical Left
D1    /4     SHL r/m32,1             Shift Logical Left
D3    /4     SHL r/m32,CL            Shift Logical Left
C1    /4 ib  SHL r/m32,imm8          Shift Logical Left
D0    /5     SHR r/m8,1              Shift Logical Right
D2    /5     SHR r/m8,CL             Shift Logical Right
C0    /5 ib  SHR r/m8,imm8           Shift Logical Right
D1    /5     SHR r/m32,1             Shift Logical Right
D3    /5     SHR r/m32,CL            Shift Logical Right
C1    /5 ib  SHR r/m32,imm8          Shift Logical Right
1C       ib  SBB AL,imm8             Subtract with borrow 
1D       id  SBB EAX,imm32           Subtract with borrow