📄 pentium.txt
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DA /0 FIADD m32int Add m32int to ST(0) and s.r.in ST(0)
DE /0 FIADD m16int Add m16int to ST(0) and s.r.in ST(0)
DF /4 FBLD m80bcd Convert m80BCD to real and push
DF /6 FBSTP m80bcd Store ST(0) in m80bcd and pop ST(0)
D9 E0 FCHS Complements sign of ST(0)
9B DB E2 FCLEX Clear f.e.f. after checking for ..
DB E2 FNCLEX Clear f.e.f. without checking for ..
DA C0+i FCMOVB ST(0),ST(i) Move if below
DA C8+i FCMOVE ST(0),ST(i) Move if equal
DA D0+i FCMOVBE ST(0),ST(i) Move if below or equal
DA D8+i FCMOVU ST(0),ST(i) Move if unordered
DB C0+i FCMOVNB ST(0),ST(i) Move if not below
DB C8+i FCMOVNE ST(0),ST(i) Move if not equal
DB D0+i FCMOVNBE ST(0),ST(i) Move if not below or equal
DB D8+i FCMOVNU ST(0),ST(i) Move if not unordered
D8 /2 FCOM m32real Compare ST(0) with m32real.
DC /2 FCOM m64real Compare ST(0) with m64real.
D8 D0+i FCOM ST(i) Compare ST(0) with ST(i).
D8 D1 FCOM Compare ST(0) with ST(1).
D8 /3 FCOMP m32real Compare ST(0) with m32real,pop r.stack.
DC /3 FCOMP m64real Compare ST(0) with m64real,pop r.stack.
D8 D8+i FCOMP ST(i) Compare ST(0) with ST(i), pop
D8 D9 FCOMP Compare ST(0) with ST(1), pop
DE D9 FCOMPP Compare ST(0) with ST(1), pop pop
DB F0+i FCOMI ST,ST(i) Compare ST(0) with ST(i), set status flags
DF F0+i FCOMIP ST,ST(i) Compare ST(0) with ST(i), set s.f. ,pop
DB E8+i FUCOMI ST,ST(i) Compare ST(0) with ST(i), check o.v.set s.f.
DF E8+i FUCOMIP ST,ST(i) Compare ST(0) with ST(i), check ovssf pop
D9 FF FCOS Replace ST(0) with its cosine
D9 F6 FDECSTP Decrement TOP field in FPU status word.
D8 /6 FDIV m32real Divide ST(0) by m32real and s.r.in ST(0)
DC /6 FDIV m64real Divide ST(0) by m64real and s.r.in ST(0)
D8 F0+i FDIV ST(0),ST(i) Divide ST(0) by ST(i) and s.r.in ST(0)
DC F8+i FDIV ST(i),ST(0) Divide ST(i) by ST(0) and s.r.in ST(i)
DE F8+i FDIVP ST(i),ST(0) Divide ST(i) by ST(0), s.r.in ST(i) pop
DE F9 FDIVP Divide ST(1) by ST(0), s.r.in ST(1) pop
DA /6 FIDIV m32int Divide ST(0) by m32int and s.r.in ST(0)
DE /6 FIDIV m16int Divide ST(0) by m64int and s.r.in ST(0)
D8 /7 FDIVR m32real Divide m32real by ST(0) and s.r.in ST(0)
DC /7 FDIVR m64real Divide m64real by ST(0) and s.r.in ST(0)
D8 F8+i FDIVR ST(0),ST(i) Divide ST(i) by ST(0) and s.r.in ST(0)
DC F0+i FDIVR ST(i),ST(0) Divide ST(0) by ST(i) and s.r.in ST(i)
DE F0+i FDIVRP ST(i),ST(0) Divide ST(0) by ST(i), s.r.in ST(i) pop
DE F1 FDIVRP Divide ST(0) by ST(1), s.r.in ST(1) pop
DA /7 FIDIVR m32int Divide m32int by ST(0) and s.r.in ST(0)
DE /7 FIDIVR m16int Divide m64int by ST(0) and s.r.in ST(0)
DD C0+i FFREE ST(i) Sets tag for ST(i) to empty
DE /2 FICOM m16int Compare ST(0) with m16int
DA /2 FICOM m32int Compare ST(0) with m32int
DE /3 FICOMP m16int Compare ST(0) with m16int and pop
DA /3 FICOMP m32int Compare ST(0) with m32int and pop
DF /0 FILD m16int Push m16int
DB /0 FILD m32int Push m32int
DF /5 FILD m64int Push m64int
D9 F7 FINCSTP Increment the TOP field FPU status r.
9B DB E3 FINIT Initialize FPU after ...
DB E3 FNINIT Initialize FPU without ...
DF /2 FIST m16int Store ST(0) in m16int
DB /2 FIST m32int Store ST(0) in m32int
DF /3 FISTP m16int Store ST(0) in m16int and pop
DB /3 FISTP m32int Store ST(0) in m32int and pop
DF /7 FISTP m64int Store ST(0) in m64int and pop
D9 /0 FLD m32real Push m32real
DD /0 FLD m64real Push m64real
DB /5 FLD m80real Push m80real
D9 C0+i FLD ST(i) Push ST(i)
D9 E8 FLD1 Push +1.0
D9 E9 FLDL2T Push log2 10
D9 EA FLDL2E Push log2 e
D9 EB FLDPI Push pi
D9 EC FLDLG2 Push log10 2
D9 ED FLDLN2 Push loge 2
D9 EE FLDZ Push +0.0
D9 /5 FLDCW m2byte Load FPU control word from m2byte
D9 /4 FLDENV m14/28byte Load FPU environment from m14/m28
D8 /1 FMUL m32real Multiply ST(0) by m32real and s.r.in ST(0)
DC /1 FMUL m64real Multiply ST(0) by m64real and s.r.in ST(0)
D8 C8+i FMUL ST(0),ST(i) Multiply ST(0) by ST(i) and s.r.in ST(0)
DC C8+i FMUL ST(i),ST(0) Multiply ST(i) by ST(0) and s.r.in ST(i)
DE C8+i FMULP ST(i),ST(0) Multiply ST(i) by ST(0), s.r.in ST(i) pop
DE C9 FMULP Multiply ST(1) by ST(0), s.r.in ST(1) pop
DA /1 FIMUL m32int Multiply ST(0) by m32int and s.r.in ST(0)
DE /1 FIMUL m16int Multiply ST(0) by m16int and s.r.in ST(0)
D9 D0 FNOP No operation is performed
D9 F3 FPATAN Repalces ST(1) with arctan(ST(1)/ST(0)) pop
D9 F8 FPREM Replaces ST(0) with rem (ST(0)/ST(1))
D9 F5 FPREM1 Replaces ST(0) with IEEE rem(ST(0)/ST(1))
D9 F2 FPTAN Replaces ST(0) with its tangent push 1.0
D9 FC FRNDINT Round ST(0) to an integer
DD /4 FRSTOR m94/108byte Load FPU status from m94 or m108 byte
9B DD /6 FSAVE m94/108byte Store FPU status to m94 or m108
DD /6 FNSAVE m94/108byte Store FPU environment to m94 or m108
D9 FD FSCALE Scale ST(0) by ST(1)
D9 FE FSIN Replace ST(0) with its sine
D9 FB FSINCOS Compute sine and consine of ST(0) s push c
D9 FA FSQRT square root of ST(0)
D9 /2 FST m32real Copy ST(0) to m32real
DD /2 FST m64real Copy ST(0) to m64real
DD D0+i FST ST(i) Copy ST(0) to ST(i)
D9 /3 FSTP m32real Copy ST(0) to m32real and pop
DD /3 FSTP m64real Copy ST(0) to m64real and pop
DB /7 FSTP m80real Copy ST(0) to m80real and pop
DD D8+i FSTP ST(i) Copy ST(0) to ST(i) and pop
9B D9 /7 FSTCW m2byte Store FPU control word
D9 /7 FNSTCW m2byte Store FPU control word without
9B D9 /6 FSTENV m14/28byte Store FPU environment
D9 /6 FNSTENV m14/28byte Store FPU env without
9B DD /7 FSTSW m2byte Store FPU status word at m2byte after
9B DF E0 FSTSW AX Store FPU status word in AX after
DD /7 FNSTSW m2byte Store FPU status word at m2byte without
DF E0 FNSTSW AX Store FPU status word in AX without
D8 /4 FSUB m32real Sub m32real from ST(0) and s.r.in ST(0)
DC /4 FSUB m64real Sub m64real from ST(0) and s.r.in ST(0)
D8 E0+i FSUB ST(0),ST(i) Sub ST(i) from ST(0) and s.r.in ST(0)
DC E8+i FSUB ST(i),ST(0) Sub ST(0) from ST(i) and s.r.in ST(i)
DE E8+i FSUBP ST(i),ST(0) Sub ST(0) from ST(i), s.r.in ST(i) pop
DE E9 FSUBP Sub ST(0) from ST(1), s.r.in ST(1) pop
DA /4 FISUB m32int Sub m32int from ST(0) and s.r.in ST(0)
DE /4 FISUB m16int Sub m16int from ST(0) and s.r.in ST(0)
D8 /5 FSUBR m32real Sub ST(0) from m32real and s.r.in ST(0)
DC /5 FSUBR m64real Sub ST(0) from m64real and s.r.in ST(0)
D8 E8+i FSUBR ST(0),ST(i) Sub ST(0) from ST(i) and s.r.in ST(0)
DC E0+i FSUBR ST(i),ST(0) Sub ST(i) from ST(0) and s.r.in ST(i)
DE E0+i FSUBRP ST(i),ST(0) Sub ST(i) from ST(0), s.r. in ST(i) pop
DE E1 FSUBRP Sub ST(1) from ST(0), s.r.in ST(1) pop
DA /5 FISUBR m32int Sub ST(0) from m32int and s.r.in ST(0)
DE /5 FISUBR m16int Sub ST(0) from m16int and s.r.in ST(0)
D9 E4 FTST Compare ST(0) with 0.0
DD E0+i FUCOM ST(i) Compare ST(0) with ST(i)
DD E1 FUCOM Compare ST(0) with ST(1)
DD E8+i FUCOMP ST(i) Compare ST(0) with ST(i) and pop
DD E9 FUCOMP Compare ST(0) with ST(1) and pop
DA E9 FUCOMPP Compare ST(0) with ST(1) and pop pop
D9 E5 FXAM Classify value or number in ST(0)
D9 C8+i FXCH ST(i) Exchange ST(0) and ST(i)
D9 C9 FXCH Exchange ST(0) and ST(1)
D9 F4 FXTRACT Seperate value in ST(0) exp. and sig.
D9 F1 FYL2X Replace ST(1) with ST(1)*log2ST(0) and pop
D9 F9 FYL2XP1 Replace ST(1) with ST(1)*log2(ST(0)+1) pop
F4 HLT Halt
F6 /7 IDIV r/m8 Divide
F7 /7 IDIV r/m32 Divide
F6 /5 IMUL r/m8 Multiply
F7 /5 IMUL r/m32 Multiply
0F AF /r IMUL r32,r/m32 Multiply
6B /r ib IMUL r32,r/m32,imm8 Multiply
6B /r ib IMUL r32,imm8 Multiply
69 /r id IMUL r32,r/m32,imm32 Multiply
69 /r id IMUL r32,imm32 Multiply
E4 ib IN AL,imm8 Input byte from imm8 I/O port address into AL
E5 ib IN EAX,imm8 Input byte from imm8 I/O port address into EAX
EC IN AL,DX Input byte from I/O port in DX into AL
ED IN EAX,DX Input doubleword from I/O port in DX into EAX
FE /0 INC r/m8 Increment 1
FF /0 INC r/m32 Increment 1
40+rd INC r32 Increment register by 1
6C INS m8 Input byte from I/O(DX) into ES:(E)DI
6D INS m32 Input dw from I/O(DX) into ES:(E)DI
CC INT 3 Interrupt 3--trap to debugger
CD ib INT imm8 Interrupt vector number (imm8)
CE INTO Interrupt 4--if overflow flag is 1
0F 08 INVD Flush internal caches
0F 01 /7 INVLPG m Invalidate TLB Entry for page (m)
CF IRETD Interrupt return(32)
77 cb JA rel8 Jump short if above
73 cb JAE rel8 Jump short if above or equal
76 cb JBE rel8 Jump short if below or equal
72 cb JC rel8 Jump short if carry
E3 cb JECXZ rel8 Jump short if ECX register is 0
74 cb JE rel8 Jump short if equal
7F cb JG rel8 Jump short if greater
7D cb JGE rel8 Jump short if greater or equal
7C cb JL rel8 Jump short if less
7E cb JLE rel8 Jump short if less or equal
75 cb JNE rel8 Jump short if not equal
71 cb JNO rel8 Jump short if not overflow
79 cb JNS rel8 Jump short if not sign
70 cb JO rel8 Jump short if overflow
7A cb JPE rel8 Jump short if parity even
7B cb JPO rel8 Jump short if parity odd
78 cb JS rel8 Jump short if sign
0F 87 cd JA rel32 Jump near if above
0F 83 cd JAE rel32 Jump near if above or equal
0F 82 cd JB rel32 Jump near if below
0F 86 cd JBE rel32 Jump near if below or equal
0F 84 cd JE rel32 Jump near if equal
0F 8F cd JG rel32 Jump near if greater
0F 8D cd JGE rel32 Jump near if greater or equal
0F 8C cd JL rel32 Jump near if less
0F 8E cd JLE rel32 Jump near if less or equal
0F 85 cd JNE rel32 Jump near if not equal
0F 81 cd JNO rel32 Jump near if not overflow
0F 89 cd JNS rel32 Jump near if not sign
0F 80 cd JO rel32 Jump near if overflow
0F 8A cd JPE rel32 Jump near if parity even
0F 8B cd JPO rel32 Jump near if parity odd
0F 88 cd JS rel32 Jump near if sign
EB cb JMP rel8 Jump short, relative,
E9 cd JMP rel32 Jump near, relative,
FF /4 JMP r/m32 Jump near, abs.ind.in r/m32
EA cp JMP ptr16:32 Jump far, abs.add given in operand
FF /r JMP m16:32 Jump far, abs.ind.in m16:32
9F LAHF Load Status Flags into AH
0F 02 /r LAR r32,r/m32 Load Access Rights Byte
C5 /r LDS r32,m16:32 Load DS:r32 with far ptr
8D /r LEA r32,m Load effective address
C9 LEAVE Set ESP to EBP, then pop EBP
C4 /r LES r32,m16:32 Load ES:r32 with far ptr
0F B4 /r LFS r32,m16:32 Load FS:r32 with far ptr
0F B5 /r LGS r32,m16:32 Load GS:r32 with far ptr
0F 01 /2 LGDT m16&32 Load m into GDTR
0F 01 /3 LIDT m16&32 Load m into IDTR
0F 00 /2 LLDT r/m16 Load segment selector r/m16 into LDTR
0F 01 /6 LMSW r/m16 Load r/m16 in machine status word of CR0
F0 LOCK Asserts LOCK signal for duration ..
AC LODS m8 Load byte at address DS:(E)SI into AL
AD LODS m32 Load dword at address DS:(E)SI into EAX
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