📄 pentium.txt
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The Complete Pentium Instruction Set Table
(32 Bit Addressing Mode Only)
by Sang Cho
**********************************************
Explanation of the Notation used in this Table
**********************************************
/digit -- A digit between 0 and 7 indicates that the ModR/M byte of the instruction uses
only the r/m (register or memory) operand. The reg field contains the digit
that provides an extension to the instruction's opcode.
/r -- Indicates that the ModR/M byte of the instruction contains both a register operand
and an r/m operand.
cb -- A relative byte offset from the next instruction for JMP, CALL etc.
cw -- A relative word offset from the next instruciton for JMP, CALL etc.
cd -- A relative doubleword offset from the next instruction for JMP, CALL etc.
cp -- An absolute far pointer for JMP, CALL etc.
ib, iw, id
-- 1-byte (ib), 2-byte (iw), or 4-byte (id) immediate operand
+rb, +rw, +rd
-- register code, from 0 through 7, added to an opcode byte.
rb rw rd
----------------------
AL = 0 AX = 0 EAX = 0
CL = 1 CX = 1 ECX = 1
DL = 2 DX = 2 EDX = 2
BL = 3 BX = 3 EBX = 3
AH = 4 SP = 4 ESP = 4
CH = 5 BP = 5 EBP = 5
DH = 6 SI = 6 ESI = 6
BH = 7 DI = 7 EDI = 7
+i -- A number used in floating-point instructions when one of the operands is ST(i) from
the FPU register stack.
rel8 -- A relative address in the range from -128 to 127 bytes from the end of the instruction.
rel16 and rel32
-- A relative address within the same code segment as the instruction assembled.
ptr16:16 and ptr16:32
-- A far pointer, typically in a code segment different from that of the instruction.
r8 -- One of the byte general-purpose registers.
r16 -- One of the word general-purpose registers.
r32 -- One of the doubleword general-purpose registers.
imm8 -- An immediate byte value.
imm16 -- An immediate word value.
imm32 -- An immediate doubleword value.
r/m8 -- A byte general-purpose register, or a byte from memory.
r/m16 -- A word general-purpose register, or a word memory operand.
r/m32 -- A doubleword general-purpose register, or a doubleword memory operand.
m -- A 16- or 32-bit operand in memory.
m8 -- A byte operand in memory, pointed to by the DS:(E)SI or ES:(E)DI registers.
Used with the string instructions and the XLAT instruction.
m16 -- A word operand in memory, pointed to by the DS:(E)SI or ES:(E)DI registers.
Used only with the string instructions.
m32 -- A doubleword operand in memory, pointed to by the DS:(E)SI or ES:(E)DI registers.
Used only with the string instructions.
m64 -- A memory quadword operand in memory. Used only with the CMPXCHG8B instruction.
m16:16, m16:32
-- A memory operand containing a far pointer composed of two numbers.
The number to the left of the colon corresponds to the pointer's segment selector.
The number to the right corresponds to its offset.
m16&32, m16&16, m32&32
-- A memory operand consisting of data item pairs whose
sizes are indicated on the left and the right side of the ampersand.
All memory addressing modes are allowed. The m16&16 and m32&32 operands are used
by the BOUND instruction to provide an operand containing an upper and lower bounds
for array indices. The m16&32 operand is used by LIDT and LGDT to provide
a word with which to load the limit field, and a doubleword with which to load
the base field of the corresponding GDTR and IDTR registers.
moffs8, moffs16, moffs32
-- A simple memory variable (memory offset) of type byte,
word, or doubleword used by some variants of the MOV instruction.
The actual address is given by a simple offset relative to the segment base.
No ModR/M byte is used in the instruction. The number shown with moffs indicates
its size, which is determined by the address-size attribute of the instruction.
Sreg -- A segment register. The segment register bit assignments are ES=0, CS=1, SS=2,
DS=3, FS=4, and GS=5.
m32real, m64real, m80real
-- A single-, double-, and extended-real floating-point operand in memory.
m16int, m32int, m64int
-- A word-, short-, and long-integer floating-point operand in memory.
ST or ST(0)
-- The top element of the FPU register stack.
ST(i) -- The i th element from the top of the FPU register stack. (i = 0 through 7)
mm -- An MMX register. The 64-bit MMX registers are: MM0 through MM7.
mm/m32 -- The low order 32 bits of an MMX register or a 32-bit memory operand.
mm/m64 -- An MMX register or a 64-bit memory operand.
Alphabetical Listing
===============================================================================
Opcode,Data Instruction Explanation
-------------------------------------------------------------------------------
37 AAA ASCII adjust AL after addition
D5 0A AAD ASCII adjust AX before division
D4 0A AAM ASCII adjust AX after multiplication
3F AAS ASCII adjust AL after subtraction
14 ib ADC AL,imm8 Add with carry
15 id ADC EAX,imm32 Add with carry
80 /2 ib ADC r/m8,imm8 Add with carry
81 /2 id ADC r/m32,imm32 Add with carry
83 /2 ib ADC r/m32,imm8 Add with carry
10 /r ADC r/m8,r8 Add with carry
11 /r ADC r/m32,r32 Add with carry
12 /r ADC r8,r/m8 Add with carry
13 /r ADC r32,r/m32 Add with carry
04 ib ADD AL,imm8 Add
05 id ADD EAX,imm32 Add
80 /0 ib ADD r/m8,imm8 Add
81 /0 id ADD r/m32,imm32 Add
83 /0 ib ADD r/m32,imm8 Add
00 /r ADD r/m8,r8 ADD
01 /r ADD r/m32,r32 ADD
02 /r ADD r8,r/m8 ADD
03 /r ADD r32,r/m32 ADD
24 ib AND AL,imm8 AND
25 id AND EAX,imm32 AND
80 /4 ib AND r/m8,imm8 AND
81 /4 id AND r/m32,imm32 AND
83 /4 ib AND r/m32,imm8 AND
20 /r AND r/m8,r8 AND
21 /r AND r/m32,r32 AND
22 /r AND r8,r/m8 AND
23 /r AND r32,r/m32 AND
63 /r ARPL r/m16,r16 Adjust Request Privilege Level of Sel.
62 /r BOUND r32,m32&32 Check Array Index Against Bounds
0F BC /r BSF r32,r/m32 Bit scan forward on r/m32
0F BD /r BSR r32,r/m32 Bit scan reverse on r/m32
0F C8+rd BSWAP r32 Reverses the byte order of a r32
0F A3 /r BT r/m32,r32 Bit Test
0F BA /4 ib BT r/m32,imm8 Bit Test
0F BB /r BTC r/m32,r32 Bit Test and Complement
0F BA /7 ib BTC r/m32,imm8 Bit Test and Complement
0F B3 /r BTR r/m32,r32 Bit Test and Clear
0F BA /6 ib BTR r/m32,imm8 Bit Test and Clear
0F AB /r BTS r/m32,r32 Bit Test and Set
0F BA /5 ib BTS r/m32,imm8 Bit Test and Set
E8 cd CALL rel32 Call near, rel to n.inst
FF /2 CALL r/m32 Call near, abs.ind.add. given in r/m32
9A cp CALL ptr16:32 Call far, abs.add. given in operand
FF /3 CALL m16:32 Call far, abs.ind.add. given in m16:32
98 CBW Convert Byte to Word
99 CWD Convert Word to Doubleword
99 CDQ Convert Doubleword to Quadword
F8 CLC Clear CF flag
FC CLD Clear DF flag
FA CLI Clear interrupt flag
0F 06 CLTS Clear Task-Switched Flag in Control Reg. Zero
F5 CMC Complement CF flag
0F 47 /r CMOVA r32,r/m32 Move if above
0F 43 /r CMOVAE r32,r/m32 Move if above or equal
0F 42 /r CMOVB r32,r/m32 Move if below
0F 46 /r CMOVBE r32,r/m32 Move if below or equal
0F 42 /r CMOVC r32,r/m32 Move if carry
0F 44 /r CMOVE r32,r/m32 Move if equal
0F 4F /r CMOVG r32,r/m32 Move if greater
0F 4D /r CMOVGE r32,r/m32 Move if greater or equal
0F 4C /r CMOVL r32,r/m32 Move if less
0F 4E /r CMOVLE r32,r/m32 Move if less or equal
0F 46 /r CMOVNA r32,r/m32 Move if not above
0F 42 /r CMOVNAE r32,r/m32 Move if not above or equal
0F 43 /r CMOVNB r32,r/m32 Move if not below
0F 47 /r CMOVNBE r32,r/m32 Move if not below or equal
0F 43 /r CMOVNC r32,r/m32 Move if not carry
0F 45 /r CMOVNE r32,r/m32 Move if not equal
0F 4E /r CMOVNG r32,r/m32 Move if not greater
0F 4C /r CMOVNGE r32,r/m32 Move if not greater or equal
0F 4D /r CMOVNL r32,r/m32 Move if not less
0F 4F /r CMOVNLE r32,r/m32 Move if not less or equal
0F 41 /r CMOVNO r32,r/m32 Move if not overflow
0F 4B /r CMOVNP r32,r/m32 Move if not parity
0F 49 /r CMOVNS r32,r/m32 Move if not sign
0F 45 /r CMOVNZ r32,r/m32 Move if not zero
0F 40 /r CMOVO r32,r/m32 Move if overflow
0F 4A /r CMOVP r32,r/m32 Move if parity
0F 4A /r CMOVPE r32,r/m32 Move if parity even
0F 4B /r CMOVPO r32,r/m32 Move if parity odd
0F 48 /r CMOVS r32,r/m32 Move if sign
0F 44 /r CMOVZ r32,r/m32 Move if zero
3C ib CMP AL,imm8 Compare
3D id CMP EAX,imm32 Compare
80 /7 ib CMP r/m8,imm8 Compare
81 /7 id CMP r/m32,imm32 Compare
83 /7 ib CMP r/m32,imm8 Compare
38 /r CMP r/m8,r8 Compare
39 /r CMP r/m32,r32 Compare
3A /r CMP r8,r/m8 Compare
3B /r CMP r32,r/m32 Compare
A6 CMPSB Compare byte at DS:(E)SI with ES:(E)DI
A7 CMPSD Compare dw at DS:(E)SI with ES:(E)DI
0F B0 /r CMPXCHG r/m8,r8 Compare and Exchange
0F B1 /r CMPXCHG r/m32,r32 Compare and Exchange
0F C7 /1 m64 CMPXCHG8B m64 Compare and Exchange
0F A2 CPUID EAX := Processor id.info.
27 DAA Decimal adjust AL after addition
2F DAS Decimal adjust AL after subtraction
FE /1 DEC r/m8 Decrement r/m8 by 1
FF /1 DEC r/m32 Decrement r/m32 by 1
48+rd DEC r32 Decrement r32 by 1
F6 /6 DIV r/m8 Unsigned divide AX by r/m8
F7 /6 DIV r/m16 Unsigned divide DX:AX by r/m16
F7 /6 DIV r/m32 Unsigned divide EDX:EAX by r/m32
0F 77 EMMS Set the FP tag word to empty
C8 iw 00 ENTER imm16,0 Create a stack frame for a procedure
C8 iw 01 ENTER imm16,1 Create a nested stack frame for a proc.
C8 iw ib ENTER imm16,imm8 Create a nested stack frame for a proc.
D9 F0 F2XM1 Replace ST(0) with 2**ST(0) - 1
D9 E1 FABS Replace ST(0) with its absolute value
D8 /0 FADD m32real Add m32real to ST(0) and s.r. in ST(0)
DC /0 FADD m64real Add m64real to ST(0) and s.r.in ST(0)
D8 C0+i FADD ST(0),ST(i) Add ST(0) to ST(i) and s.r.in ST(0)
DC C0+i FADD ST(i),ST(0) Add ST(i) to ST(0) and s.r. in ST(i)
DE C0+i FADDP ST(i),ST(0) Add ST(0) to ST(i), s.r.in ST(i),pop r.stack
DE C1 FADDP Add ST(0) to ST(1), s.r.in ST(1),pop r.stack
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