10分钟学会pld设计—2 编译和布线.htm
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has user pin or logic cell assignments, but never been compiled before.
For best fitting results, let the compiler choose the first set of
assignments instead”，这是因为在管脚指定之前没有compile，你只要再点save &
compile就可以了</SPAN></P>
<P align=left><SPAN class=font10 lang=EN-US
mso-bidi-font-size:12.0pt;font-family:宋体;color:black?><BR><IMG
height=118 src="10分钟学会PLD设计—2 编译和布线.files/image056.jpg" width=553
border=0 v:shapes="_x0000_i1060"> <O:P></O:P></SPAN></P>
<P align=left><SPAN class=font10 lang=EN-US mso-bidi-font-family:Arial?
mso-bidi-font-size:9.0pt;font-family:宋体;>MAX+PLUS II </SPAN><SPAN
class=font10
mso-bidi-font-size:9.0pt;font-family:宋体?>编译器将检查项目是否有错，并对项目进行逻辑综合，然后对设计进行布局布线，放到一个</SPAN><SPAN
class=font10 lang=EN-US mso-bidi-font-family:Arial?
mso-bidi-font-size:9.0pt;font-family:宋体;>Altera </SPAN><SPAN
class=font10
mso-bidi-font-size:9.0pt;font-family:宋体?>器件中，同时将产生报告文件、编程文件和用于时间仿真用的输出文件</SPAN><SPAN
class=font10 lang=EN-US mso-bidi-font-size:12.0pt;font-family:宋体;
display:none;mso-hide:all;mso-font-kerning:0pt?><O:P></O:P></SPAN></P>
<P align=left><SPAN class=font10 lang=EN-US mso-bidi-font-size:
12.0pt;font-family:宋体?><O:P><SPAN class=font10
mso-bidi-font-size:9.0pt;font-family:宋体?>逻辑综合：就是把HDL语言或原理图翻译成最基本的与或非门的连接关系</SPAN></O:P></SPAN></P>
<P align=left><SPAN class=font10 lang=EN-US mso-bidi-font-size:
12.0pt;font-family:宋体?><O:P><SPAN class=font10
mso-bidi-font-size:9.0pt;font-family:宋体?>布局布线：把这种<SPAN class=font10
lang=EN-US mso-bidi-font-size: 12.0pt;font-family:宋体?><SPAN class=font10
mso-bidi-font-size:9.0pt;font-family:宋体?>与或非门的</SPAN></SPAN>连接关系用芯片的内部的<SPAN
class=font10 lang=EN-US mso-bidi-font-size: 12.0pt;font-family:宋体?><SPAN
class=font10
mso-bidi-font-size:9.0pt;font-family:宋体?>可编程</SPAN></SPAN>结构和连线来实现</SPAN></O:P></SPAN></P>
<P align=left><SPAN class=font10 lang=EN-US mso-bidi-font-size:
12.0pt;font-family:宋体?><O:P></O:P></SPAN></P>
<P align=left><SPAN class=font10 font-family:宋体;color:black?
mso-bidi-font-size:12.0pt;>如果设计正确，将下图所示，点确认<SPAN lang=EN-US><BR><IMG
height=238 src="10分钟学会PLD设计—2 编译和布线.files/image058.jpg" width=553
border=0 v:shapes="_x0000_i1061"> <O:P></O:P></SPAN></SPAN></P>
<P align=left><SPAN class=font10 font-family:宋体;color:black?
mso-bidi-font-size:12.0pt;>编译后可以看到<SPAN
lang=EN-US>IO在芯片上的分布：MAX+plusII-> Froorplan
Editor<O:P></O:P></SPAN></SPAN></P>
<P align=left><SPAN class=font10 lang=EN-US
12.0pt;font-family:宋体;color:black? mso-bidi-font-size:><IMG height=314
src="10分钟学会PLD设计—2 编译和布线.files/image059.jpg" width=248 border=0
v:shapes="_x0000_i1062"> <O:P></O:P></SPAN></P>
<P align=left><SPAN class=font10 lang=EN-US
mso-ansi-language:EN-US;mso-fareast-language:ZH-CN;mso-bidi-language:AR-SA?
Roman?;color:black;mso-font-kerning:1.0pt; New
宋体;mso-bidi-font-family:?Times
mso-bidi-font-size:12.0pt;font-family:><BR
style="PAGE-BREAK-BEFORE: always" clear=all></SPAN></P>
<P align=left><SPAN class=font10 font-family:宋体;color:black?
mso-bidi-font-size:12.0pt;>将弹出一窗口如下图<SPAN
lang=EN-US><O:P></O:P></SPAN></SPAN></P>
<P align=left><SPAN class=font10 lang=EN-US
12.0pt;font-family:宋体;color:black? mso-bidi-font-size:><IMG height=158
src="10分钟学会PLD设计—2 编译和布线.files/image061.jpg" width=324 border=0
v:shapes="_x0000_i1063"> <O:P></O:P></SPAN></P>
<P align=left><SPAN class=font10 font-family:宋体;color:black?
mso-bidi-font-size:12.0pt;>双击空白处，可以看到下图所示<SPAN
lang=EN-US>IO在芯片EPM7128SLC84上的布局<O:P></O:P></SPAN></SPAN></P>
<P align=left><SPAN class=font10 lang=EN-US
12.0pt;font-family:宋体;color:black? mso-bidi-font-size:><IMG height=473
src="10分钟学会PLD设计—2 编译和布线.files/image063.jpg" width=553 border=0
v:shapes="_x0000_i1064"> <O:P></O:P></SPAN></P>
<P align=left><SPAN class=font10 lang=EN-US
mso-ansi-language:EN-US;mso-fareast-language:ZH-CN;mso-bidi-language:AR-SA?
Roman?;color:black;mso-font-kerning:1.0pt; New
宋体;mso-bidi-font-family:?Times
mso-bidi-font-size:12.0pt;font-family:><BR
style="PAGE-BREAK-BEFORE: always" clear=all></SPAN></P>
<P align=left><SPAN class=font10 lang=EN-US
12.0pt;font-family:宋体;color:black? mso-bidi-font-size:>创建一个设计的符号<SPAN
lang=EN-US><O:P></O:P></SPAN></SPAN></P>
<P align=left><SPAN class=font10 font-family:宋体?
mso-bidi-font-size:10.0pt;>（此和本设计无关，仅供其他设计在高层调用）</SPAN><SPAN
class=font10 lang=EN-US
mso-bidi-font-size:12.0pt;font-family:宋体?><O:P></O:P></SPAN></P>
<P align=left><SPAN class=font10
mso-bidi-font-size:10.0pt;font-family:宋体?>在</SPAN><SPAN class=font10
Arial? mso-bidi-font-size:10.0pt;font-family:宋体;mso-bidi-font-family:>
<SPAN lang=EN-US>File</SPAN></SPAN><SPAN class=font10
mso-bidi-font-size:10.0pt;font-family:宋体?>菜单中选择</SPAN><SPAN class=font10
lang=EN-US Arial?
mso-bidi-font-size:10.0pt;font-family:宋体;mso-bidi-font-family:> Create
Default Symbol </SPAN><SPAN class=font10
mso-bidi-font-size:10.0pt;font-family:宋体?>项，即可创建一个设计的符号。该符号可被高层设计调用。<SPAN
lang=EN-US><O:P></O:P></SPAN></SPAN></P>
<P align=left><SPAN class=font10 lang=EN-US
mso-bidi-font-size:10.0pt;font-family:宋体?><IMG height=263
src="10分钟学会PLD设计—2 编译和布线.files/image064.jpg" width=352>
<O:P></O:P></SPAN></P>
<P align=left><SPAN class=font10
mso-bidi-font-size:10.0pt;font-family:宋体?>此时会产生一个<SPAN
lang=EN-US>COMPILE窗口，直接点Start,完成后点确认<O:P></O:P></SPAN></SPAN></P>
<P align=left><SPAN class=font10 lang=EN-US mso-bidi-font-size:
10.0pt;font-family:宋体?><IMG height=196
src="10分钟学会PLD设计—2 编译和布线.files/image067.jpg" width=553 border=0
v:shapes="_x0000_i1066"></SPAN></P>
<P align=left> </P>
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<P class=font10 align=left>下面您可以继续学习：</P>
<P class=font10 align=left><A class=font10
href="http://www.fpga.com.cn/rumen/simulation.htm">10分钟学会PLD设计3
－设计的仿真</A></P>
<P class=font10 align=left><A class=font10
href="http://www.fpga.com.cn/rumen/download.htm">10分钟学会PLD设计4
－下载</A></P>
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