sfr80144.h

一款收款机C源代码！因为是几年前的代码了

    X-Y control register
------------------------------------------------------*/
union byte_def xyc_addr;
#define     xyc     xyc_addr.byte

#define     xyc0        xyc_addr.bit.b0
#define     xyc1        xyc_addr.bit.b1

/*------------------------------------------------------
    Protect register
------------------------------------------------------*/
union byte_def prcr_addr;
#define     prcr        prcr_addr.byte

#define     prc0        prcr_addr.bit.b0    /* Enables writing to system clock control register 0 and 1 */
#define     prc1        prcr_addr.bit.b1    /* Enables writing to processor mode register 0 and 1 */
#define     prc2        prcr_addr.bit.b2    /* Enables writing to port P9 direction register and function select register A3 */

/*------------------------------------------------------
    External data bus width control register
------------------------------------------------------*/
union byte_def ds_addr;
#define     ds      ds_addr.byte

#define     ds0     ds_addr.bit.b0
#define     ds1     ds_addr.bit.b1
#define     ds2     ds_addr.bit.b2
#define     ds3     ds_addr.bit.b3

/*------------------------------------------------------
    Main clock division register
------------------------------------------------------*/
union byte_def mcd_addr;
#define     mcd     mcd_addr.byte

#define     mcd0        mcd_addr.bit.b0
#define     mcd1        mcd_addr.bit.b1
#define     mcd2        mcd_addr.bit.b2
#define     mcd3        mcd_addr.bit.b3
#define     mcd4        mcd_addr.bit.b4

/*------------------------------------------------------
    Exit priority register
------------------------------------------------------*/
union byte_def rlvl_addr;
#define     rlvl        rlvl_addr.byte

#define     rlvl0       rlvl_addr.bit.b0
#define     rlvl1       rlvl_addr.bit.b1
#define     rlvl2       rlvl_addr.bit.b2
#define     fsit        rlvl_addr.bit.b3

/*------------------------------------------------------
    Interrupt cause select register
------------------------------------------------------*/
union byte_def ifsr_addr;
#define     ifsr        ifsr_addr.byte

#define     ifsr0       ifsr_addr.bit.b0
#define     ifsr1       ifsr_addr.bit.b1
#define     ifsr2       ifsr_addr.bit.b2
#define     ifsr3       ifsr_addr.bit.b3
#define     ifsr4       ifsr_addr.bit.b4
#define     ifsr5       ifsr_addr.bit.b5

/*------------------------------------------------------
    Watchdog timer start register
------------------------------------------------------*/
union byte_def wdts_addr;
#define     wdts        wdts_addr.byte

/*------------------------------------------------------
    CRC input register
------------------------------------------------------*/
union byte_def crcin_addr;
#define     crcin       crcin_addr.byte

/*------------------------------------------------------
    Watchdog timer control register
------------------------------------------------------*/
union byte_def wdc_addr;
#define     wdc     wdc_addr.byte

#define     wdc7        wdc_addr.bit.b7     /* Prescaler select bit */

/*------------------------------------------------------
    Count start flag
------------------------------------------------------*/
union byte_def tabsr_addr;
#define     tabsr       tabsr_addr.byte

#define     ta0s        tabsr_addr.bit.b0   /* Timer A0 count start flag */
#define     ta1s        tabsr_addr.bit.b1   /* Timer A1 count start flag */
#define     ta2s        tabsr_addr.bit.b2   /* Timer A2 count start flag */
#define     ta3s        tabsr_addr.bit.b3   /* Timer A3 count start flag */
#define     ta4s        tabsr_addr.bit.b4   /* Timer A4 count start flag */
#define     tb0s        tabsr_addr.bit.b5   /* Timer B0 count start flag */
#define     tb1s        tabsr_addr.bit.b6   /* Timer B1 count start flag */
#define     tb2s        tabsr_addr.bit.b7   /* Timer B2 count start flag */

/*------------------------------------------------------
    Timer B3,4,5 count start flag
------------------------------------------------------*/
union byte_def tbsr_addr;
#define     tbsr        tbsr_addr.byte

#define     tb3s        tbsr_addr.bit.b5    /* Timer B3 count start flag */
#define     tb4s        tbsr_addr.bit.b6    /* Timer B4 count start flag */
#define     tb5s        tbsr_addr.bit.b7    /* Timer B5 count start flag */

/*------------------------------------------------------
    Three-phase PWM control regester 0
------------------------------------------------------*/
union byte_def invc0_addr;
#define     invc0       invc0_addr.byte

#define     inv00       invc0_addr.bit.b0
#define     inv01       invc0_addr.bit.b1
#define     inv02       invc0_addr.bit.b2
#define     inv03       invc0_addr.bit.b3
#define     inv04       invc0_addr.bit.b4
#define     inv05       invc0_addr.bit.b5
#define     inv06       invc0_addr.bit.b6
#define     inv07       invc0_addr.bit.b7

/*------------------------------------------------------
    Three-phase PWM control regester 1
------------------------------------------------------*/
union byte_def invc1_addr;
#define     invc1       invc1_addr.byte

#define     inv10       invc1_addr.bit.b0
#define     inv11       invc1_addr.bit.b1
#define     inv12       invc1_addr.bit.b2
#define     inv13       invc1_addr.bit.b3
#define     inv14       invc1_addr.bit.b4

/*------------------------------------------------------
    Three-phase output buffer register 0
------------------------------------------------------*/
union byte_def idb0_addr;
#define     idb0        idb0_addr.byte

#define     du0         idb0_addr.bit.b0
#define     dub0        idb0_addr.bit.b1
#define     dv0         idb0_addr.bit.b2
#define     dvb0        idb0_addr.bit.b3
#define     dw0         idb0_addr.bit.b4
#define     dwb0        idb0_addr.bit.b5

/*------------------------------------------------------
    Three-phase output buffer register 1
------------------------------------------------------*/
union byte_def idb1_addr;
#define     idb1        idb1_addr.byte

#define     du1         idb1_addr.bit.b0
#define     dub1        idb1_addr.bit.b1
#define     dv1         idb1_addr.bit.b2
#define     dvb1        idb1_addr.bit.b3
#define     dw1         idb1_addr.bit.b4
#define     dwb1        idb1_addr.bit.b5

/*------------------------------------------------------
     Dead time timer ; Use "MOV" instruction when writing to this register.
------------------------------------------------------*/
union byte_def dtt_addr;
#define     dtt     dtt_addr.byte

/*------------------------------------------------------
    Timer B2 interrupt occurrences frequency set counter ; Use "MOV" instruction when writing to this register.
------------------------------------------------------*/
union byte_def ictb2_addr;
#define     ictb2       ictb2_addr.byte

/*------------------------------------------------------
    One-shot start flag
------------------------------------------------------*/
union byte_def onsf_addr;
#define     onsf        onsf_addr.byte

#define     ta0os       onsf_addr.bit.b0    /* Timer A0 one-shot start flag */
#define     ta1os       onsf_addr.bit.b1    /* Timer A1 one-shot start flag */
#define     ta2os       onsf_addr.bit.b2    /* Timer A2 one-shot start flag */
#define     ta3os       onsf_addr.bit.b3    /* Timer A3 one-shot start flag */
#define     ta4os       onsf_addr.bit.b4    /* Timer A4 one-shot start flag */
#define     tazie       onsf_addr.bit.b5    /* Timer A4 Z-phase input valid bit */  /*99.08.30*/
#define     ta0tgl      onsf_addr.bit.b6    /* Timer A0 event/trigger select bit */
#define     ta0tgh      onsf_addr.bit.b7    /* Timer A0 event/trigger select bit */

/*------------------------------------------------------
    Clock prescaler reset flag
------------------------------------------------------*/
union byte_def cpsrf_addr;
#define     cpsrf       cpsrf_addr.byte

#define     cpsr        cpsrf_addr.bit.b7   /* Clock prescaler reset flag */

/*------------------------------------------------------
    Trigger select register
------------------------------------------------------*/
union byte_def trgsr_addr;
#define     trgsr       trgsr_addr.byte

#define     ta1tgl      trgsr_addr.bit.b0   /* Timer A1 event/trigger select bit */
#define     ta1tgh      trgsr_addr.bit.b1   /* Timer A1 event/trigger select bit */
#define     ta2tgl      trgsr_addr.bit.b2   /* Timer A2 event/trigger select bit */
#define     ta2tgh      trgsr_addr.bit.b3   /* Timer A2 event/trigger select bit */
#define     ta3tgl      trgsr_addr.bit.b4   /* Timer A3 event/trigger select bit */
#define     ta3tgh      trgsr_addr.bit.b5   /* Timer A3 event/trigger select bit */
#define     ta4tgl      trgsr_addr.bit.b6   /* Timer A4 event/trigger select bit */
#define     ta4tgh      trgsr_addr.bit.b7   /* Timer A4 event/trigger select bit */

/*------------------------------------------------------
    Up/down flag(bit symbols removed)
------------------------------------------------------*/
/* union byte_def udf_addr; */
/* #define     udf     udf_addr.byte */

// #define     ta0ud       udf_addr.bit.b0     /* Timer A0 up/down flag */ /* remove 2000.06.30 */
// #define     ta1ud       udf_addr.bit.b1     /* Timer A1 up/down flag */ /* remove 2000.06.30 */
// #define     ta2ud       udf_addr.bit.b2     /* Timer A2 up/down flag */ /* remove 2000.06.30 */
// #define     ta3ud       udf_addr.bit.b3     /* Timer A3 up/down flag */ /* remove 2000.06.30 */
// #define     ta4ud       udf_addr.bit.b4     /* Timer A4 up/down flag */ /* remove 2000.06.30 */
// #define     ta2p        udf_addr.bit.b5     /* Timer A2 two-phase pulse signal processing select bit */ /* remove 2000.06.30 */
// #define     ta3p        udf_addr.bit.b6     /* Timer A3 two-phase pulse signal processing select bit */ /* remove 2000.06.30 */
// #define     ta4p        udf_addr.bit.b7     /* Timer A4 two-phase pulse signal processing select bit */ /* remove 2000.06.30 */

/*------------------------------------------------------
    UART transmit/receive control register 2
------------------------------------------------------*/
union byte_def ucon_addr;
#define     ucon        ucon_addr.byte

#define     u0irs       ucon_addr.bit.b0    /* UART0 transmit interrupt cause select bit */
#define     u1irs       ucon_addr.bit.b1    /* UART1 transmit interrupt cause select bit */
#define     u0rrm       ucon_addr.bit.b2    /* UART0 continuous receive mode enable bit */
#define     u1rrm       ucon_addr.bit.b3    /* UART1 continuous receive mode enable bit */
                                            /* bit4&5 deleted   99.08.30    */
#define     rcsp        ucon_addr.bit.b6    /* Separate CTS~/RTS~ bit */