📄 at91rm9200.inc
字号:
AT91C_TWI_CHDIV EQU (0xFF:SHL:8) ;- (TWI) Clock High DividerAT91C_TWI_CKDIV EQU (0x7:SHL:16) ;- (TWI) Clock Divider;- -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- AT91C_TWI_TXCOMP EQU (0x1:SHL:0) ;- (TWI) Transmission CompletedAT91C_TWI_RXRDY EQU (0x1:SHL:1) ;- (TWI) Receive holding register ReaDYAT91C_TWI_TXRDY EQU (0x1:SHL:2) ;- (TWI) Transmit holding register ReaDYAT91C_TWI_SVREAD EQU (0x1:SHL:3) ;- (TWI) Slave ReadAT91C_TWI_SVACC EQU (0x1:SHL:4) ;- (TWI) Slave AccessAT91C_TWI_GCACC EQU (0x1:SHL:5) ;- (TWI) General Call AccessAT91C_TWI_OVRE EQU (0x1:SHL:6) ;- (TWI) Overrun ErrorAT91C_TWI_UNRE EQU (0x1:SHL:7) ;- (TWI) Underrun ErrorAT91C_TWI_NACK EQU (0x1:SHL:8) ;- (TWI) Not AcknowledgedAT91C_TWI_ARBLST EQU (0x1:SHL:9) ;- (TWI) Arbitration Lost;- -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- ;- -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- ;- -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- ;- *****************************************************************************;- SOFTWARE API DEFINITION FOR Multimedia Card Interface;- ***************************************************************************** ^ 0 ;- AT91S_MCIMCI_CR # 4 ;- MCI Control RegisterMCI_MR # 4 ;- MCI Mode RegisterMCI_DTOR # 4 ;- MCI Data Timeout RegisterMCI_SDCR # 4 ;- MCI SD Card RegisterMCI_ARGR # 4 ;- MCI Argument RegisterMCI_CMDR # 4 ;- MCI Command Register # 8 ;- ReservedMCI_RSPR # 16 ;- MCI Response RegisterMCI_RDR # 4 ;- MCI Receive Data RegisterMCI_TDR # 4 ;- MCI Transmit Data Register # 8 ;- ReservedMCI_SR # 4 ;- MCI Status RegisterMCI_IER # 4 ;- MCI Interrupt Enable RegisterMCI_IDR # 4 ;- MCI Interrupt Disable RegisterMCI_IMR # 4 ;- MCI Interrupt Mask Register # 176 ;- ReservedMCI_RPR # 4 ;- Receive Pointer RegisterMCI_RCR # 4 ;- Receive Counter RegisterMCI_TPR # 4 ;- Transmit Pointer RegisterMCI_TCR # 4 ;- Transmit Counter RegisterMCI_RNPR # 4 ;- Receive Next Pointer RegisterMCI_RNCR # 4 ;- Receive Next Counter RegisterMCI_TNPR # 4 ;- Transmit Next Pointer RegisterMCI_TNCR # 4 ;- Transmit Next Counter RegisterMCI_PTCR # 4 ;- PDC Transfer Control RegisterMCI_PTSR # 4 ;- PDC Transfer Status Register;- -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- AT91C_MCI_MCIEN EQU (0x1:SHL:0) ;- (MCI) Multimedia Interface EnableAT91C_MCI_MCIDIS EQU (0x1:SHL:1) ;- (MCI) Multimedia Interface DisableAT91C_MCI_PWSEN EQU (0x1:SHL:2) ;- (MCI) Power Save Mode EnableAT91C_MCI_PWSDIS EQU (0x1:SHL:3) ;- (MCI) Power Save Mode Disable;- -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- AT91C_MCI_CLKDIV EQU (0x1:SHL:0) ;- (MCI) Clock DividerAT91C_MCI_PWSDIV EQU (0x1:SHL:8) ;- (MCI) Power Saving DividerAT91C_MCI_PDCPADV EQU (0x1:SHL:14) ;- (MCI) PDC Padding ValueAT91C_MCI_PDCMODE EQU (0x1:SHL:15) ;- (MCI) PDC Oriented ModeAT91C_MCI_BLKLEN EQU (0x1:SHL:18) ;- (MCI) Data Block Length;- -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- AT91C_MCI_DTOCYC EQU (0x1:SHL:0) ;- (MCI) Data Timeout Cycle NumberAT91C_MCI_DTOMUL EQU (0x7:SHL:4) ;- (MCI) Data Timeout MultiplierAT91C_MCI_DTOMUL_1 EQU (0x0:SHL:4) ;- (MCI) DTOCYC x 1AT91C_MCI_DTOMUL_16 EQU (0x1:SHL:4) ;- (MCI) DTOCYC x 16AT91C_MCI_DTOMUL_128 EQU (0x2:SHL:4) ;- (MCI) DTOCYC x 128AT91C_MCI_DTOMUL_256 EQU (0x3:SHL:4) ;- (MCI) DTOCYC x 256AT91C_MCI_DTOMUL_1024 EQU (0x4:SHL:4) ;- (MCI) DTOCYC x 1024AT91C_MCI_DTOMUL_4096 EQU (0x5:SHL:4) ;- (MCI) DTOCYC x 4096AT91C_MCI_DTOMUL_65536 EQU (0x6:SHL:4) ;- (MCI) DTOCYC x 65536AT91C_MCI_DTOMUL_1048576 EQU (0x7:SHL:4) ;- (MCI) DTOCYC x 1048576;- -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- AT91C_MCI_SCDSEL EQU (0x1:SHL:0) ;- (MCI) SD Card SelectorAT91C_MCI_SCDBUS EQU (0x1:SHL:7) ;- (MCI) SD Card Bus Width;- -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- AT91C_MCI_CMDNB EQU (0x1F:SHL:0) ;- (MCI) Command NumberAT91C_MCI_RSPTYP EQU (0x3:SHL:6) ;- (MCI) Response TypeAT91C_MCI_RSPTYP_NO EQU (0x0:SHL:6) ;- (MCI) No responseAT91C_MCI_RSPTYP_48 EQU (0x1:SHL:6) ;- (MCI) 48-bit responseAT91C_MCI_RSPTYP_136 EQU (0x2:SHL:6) ;- (MCI) 136-bit responseAT91C_MCI_SPCMD EQU (0x7:SHL:8) ;- (MCI) Special CMDAT91C_MCI_SPCMD_NONE EQU (0x0:SHL:8) ;- (MCI) Not a special CMDAT91C_MCI_SPCMD_INIT EQU (0x1:SHL:8) ;- (MCI) Initialization CMDAT91C_MCI_SPCMD_SYNC EQU (0x2:SHL:8) ;- (MCI) Synchronized CMDAT91C_MCI_SPCMD_IT_CMD EQU (0x4:SHL:8) ;- (MCI) Interrupt commandAT91C_MCI_SPCMD_IT_REP EQU (0x5:SHL:8) ;- (MCI) Interrupt responseAT91C_MCI_OPDCMD EQU (0x1:SHL:11) ;- (MCI) Open Drain CommandAT91C_MCI_MAXLAT EQU (0x1:SHL:12) ;- (MCI) Maximum Latency for Command to respondAT91C_MCI_TRCMD EQU (0x3:SHL:16) ;- (MCI) Transfer CMDAT91C_MCI_TRCMD_NO EQU (0x0:SHL:16) ;- (MCI) No transferAT91C_MCI_TRCMD_START EQU (0x1:SHL:16) ;- (MCI) Start transferAT91C_MCI_TRCMD_STOP EQU (0x2:SHL:16) ;- (MCI) Stop transferAT91C_MCI_TRDIR EQU (0x1:SHL:18) ;- (MCI) Transfer DirectionAT91C_MCI_TRTYP EQU (0x3:SHL:19) ;- (MCI) Transfer TypeAT91C_MCI_TRTYP_BLOCK EQU (0x0:SHL:19) ;- (MCI) Block Transfer typeAT91C_MCI_TRTYP_MULTIPLE EQU (0x1:SHL:19) ;- (MCI) Multiple Block transfer typeAT91C_MCI_TRTYP_STREAM EQU (0x2:SHL:19) ;- (MCI) Stream transfer type;- -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- AT91C_MCI_CMDRDY EQU (0x1:SHL:0) ;- (MCI) Command Ready flagAT91C_MCI_RXRDY EQU (0x1:SHL:1) ;- (MCI) RX Ready flagAT91C_MCI_TXRDY EQU (0x1:SHL:2) ;- (MCI) TX Ready flagAT91C_MCI_BLKE EQU (0x1:SHL:3) ;- (MCI) Data Block Transfer Ended flagAT91C_MCI_DTIP EQU (0x1:SHL:4) ;- (MCI) Data Transfer in Progress flagAT91C_MCI_NOTBUSY EQU (0x1:SHL:5) ;- (MCI) Data Line Not Busy flagAT91C_MCI_ENDRX EQU (0x1:SHL:6) ;- (MCI) End of RX Buffer flagAT91C_MCI_ENDTX EQU (0x1:SHL:7) ;- (MCI) End of TX Buffer flagAT91C_MCI_RXBUFF EQU (0x1:SHL:14) ;- (MCI) RX Buffer Full flagAT91C_MCI_TXBUFE EQU (0x1:SHL:15) ;- (MCI) TX Buffer Empty flagAT91C_MCI_RINDE EQU (0x1:SHL:16) ;- (MCI) Response Index Error flagAT91C_MCI_RDIRE EQU (0x1:SHL:17) ;- (MCI) Response Direction Error flagAT91C_MCI_RCRCE EQU (0x1:SHL:18) ;- (MCI) Response CRC Error flagAT91C_MCI_RENDE EQU (0x1:SHL:19) ;- (MCI) Response End Bit Error flagAT91C_MCI_RTOE EQU (0x1:SHL:20) ;- (MCI) Response Time-out Error flagAT91C_MCI_DCRCE EQU (0x1:SHL:21) ;- (MCI) data CRC Error flagAT91C_MCI_DTOE EQU (0x1:SHL:22) ;- (MCI) Data timeout Error flagAT91C_MCI_OVRE EQU (0x1:SHL:30) ;- (MCI) Overrun flagAT91C_MCI_UNRE EQU (0x1:SHL:31) ;- (MCI) Underrun flag;- -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- ;- -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- ;- -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- ;- *****************************************************************************;- SOFTWARE API DEFINITION FOR USB Device Interface;- ***************************************************************************** ^ 0 ;- AT91S_UDPUDP_NUM # 4 ;- Frame Number RegisterUDP_GLBSTATE # 4 ;- Global State RegisterUDP_FADDR # 4 ;- Function Address Register # 4 ;- ReservedUDP_IER # 4 ;- Interrupt Enable RegisterUDP_IDR # 4 ;- Interrupt Disable RegisterUDP_IMR # 4 ;- Interrupt Mask RegisterUDP_ISR # 4 ;- Interrupt Status RegisterUDP_ICR # 4 ;- Interrupt Clear Register # 4 ;- ReservedUDP_RSTEP # 4 ;- Reset Endpoint Register # 4 ;- ReservedUDP_CSR # 32 ;- Endpoint Control and Status RegisterUDP_FDR # 32 ;- Endpoint FIFO Data Register;- -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- AT91C_UDP_FRM_NUM EQU (0x7FF:SHL:0) ;- (UDP) Frame Number as Defined in the Packet Field FormatsAT91C_UDP_FRM_ERR EQU (0x1:SHL:16) ;- (UDP) Frame ErrorAT91C_UDP_FRM_OK EQU (0x1:SHL:17) ;- (UDP) Frame OK;- -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- AT91C_UDP_FADDEN EQU (0x1:SHL:0) ;- (UDP) Function Address EnableAT91C_UDP_CONFG EQU (0x1:SHL:1) ;- (UDP) ConfiguredAT91C_UDP_RMWUPE EQU (0x1:SHL:2) ;- (UDP) Remote Wake Up EnableAT91C_UDP_RSMINPR EQU (0x1:SHL:3) ;- (UDP) A Resume Has Been Sent to the Host;- -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- AT91C_UDP_FADD EQU (0xFF:SHL:0) ;- (UDP) Function Address ValueAT91C_UDP_FEN EQU (0x1:SHL:8) ;- (UDP) Function Enable;- -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- AT91C_UDP_EPINT0 EQU (0x1:SHL:0) ;- (UDP) Endpoint 0 InterruptAT91C_UDP_EPINT1 EQU (0x1:SHL:1) ;- (UDP) Endpoint 0 InterruptAT91C_UDP_EPINT2 EQU (0x1:SHL:2) ;- (UDP) Endpoint 2 InterruptAT91C_UDP_EPINT3 EQU (0x1:SHL:3) ;- (UDP) Endpoint 3 InterruptAT91C_UDP_EPINT4 EQU (0x1:SHL:4) ;- (UDP) Endpoint 4 InterruptAT91C_UDP_EPINT5 EQU (0x1:SHL:5) ;- (UDP) Endpoint 5 InterruptAT91C_UDP_EPINT6 EQU (0x1:SHL:6) ;- (UDP) Endpoint 6 InterruptAT91C_UDP_EPINT7 EQU (0x1:SHL:7) ;- (UDP) Endpoint 7 InterruptAT91C_UDP_RXSUSP EQU (0x1:SHL:8) ;- (UDP) USB Suspend InterruptAT91C_UDP_RXRSM EQU (0x1:SHL:9) ;- (UDP) USB Resume InterruptAT91C_UDP_EXTRSM EQU (0x1:SHL:10) ;- (UDP) USB External Resume InterruptAT91C_UDP_SOFINT EQU (0x1:SHL:11) ;- (UDP) USB Start Of frame InterruptAT91C_UDP_WAKEUP EQU (0x1:SHL:13) ;- (UDP) USB Resume Interrupt;- -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- ;- -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- ;- -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- AT91C_UDP_ENDBUSRES EQU (0x1:SHL:12) ;- (UDP) USB End Of Bus Reset Interrupt;- -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- ;- -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- AT91C_UDP_EP0 EQU (0x1:SHL:0) ;- (UDP) Reset Endpoint 0AT91C_UDP_EP1 EQU (0x1:SHL:1) ;- (UDP) Reset Endpoint 1AT91C_UDP_EP2 EQU (0x1:SHL:2) ;- (UDP) Reset Endpoint 2AT91C_UDP_EP3 EQU (0x1:SHL:3) ;- (UDP) Reset Endpoint 3AT91C_UDP_EP4 EQU (0x1:SHL:4) ;- (UDP) Reset Endpoint 4AT91C_UDP_EP5 EQU (0x1:SHL:5) ;- (UDP) Reset Endpoint 5AT91C_UDP_EP6 EQU (0x1:SHL:6) ;- (UDP) Reset Endpoint 6AT91C_UDP_EP7 EQU (0x1:SHL:7) ;- (UDP) Reset Endpoint 7;- -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- AT91C_UDP_TXCOMP EQU (0x1:SHL:0) ;- (UDP) Generates an IN packet with data previously written in the DPRAT91C_UDP_RX_DATA_BK0 EQU (0x1:SHL:1) ;- (UDP) Receive Data Bank 0AT91C_UDP_RXSETUP EQU (0x1:SHL:2) ;- (UDP) Sends STALL to the Host (Control endpoints)AT91C_UDP_ISOERROR EQU (0x1:SHL:3) ;- (UDP) Isochronous error (Isochronous endpoints)AT91C_UDP_TXPKTRDY EQU (0x1:SHL:4) ;- (UDP) Transmit Packet ReadyAT91C_UDP_FORCESTALL EQU (0x1:SHL:5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).AT91C_UDP_RX_DATA_BK1 EQU (0x1:SHL:6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).AT91C_UDP_DIR EQU (0x1:SHL:7) ;- (UDP) Transfer DirectionAT91C_UDP_EPTYPE EQU (0x7:SHL:8) ;- (UDP) Endpoint typeAT91C_UDP_EPTYPE_CTRL EQU (0x0:SHL:8) ;- (UDP) ControlAT91C_UDP_EPTYPE_ISO_OUT EQU (0x1:SHL:8) ;- (UDP) Isochronous OUTAT91C_UDP_EPTYPE_BULK_OUT EQU (0x2:SHL:8) ;- (UDP) Bulk OUTAT91C_UDP_EPTYPE_INT_OUT EQU (0x3:SHL:8) ;- (UDP) Interrupt OUTAT91C_UDP_EPTYPE_ISO_IN EQU (0x5:SHL:8) ;- (UDP) Isochronous INAT91C_UDP_EPTYPE_BULK_IN EQU (0x6:SHL:8) ;- (UDP) Bulk INAT91C_UDP_EPTYPE_INT_IN EQU (0x7:SHL:8) ;- (UDP) Interrupt INAT91C_UDP_DTGLE EQU (0x1:SHL:11) ;- (UDP) Data ToggleAT91C_UDP_EPEDS EQU (0x1:SHL:15) ;- (UDP) Endpoint Enable DisableAT91C_UDP_RXBYTECNT EQU (0x7FF:S⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -