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AT91C_US_PAR_MULTI_DROP EQU (0x6:SHL:9) ;- (DBGU) Multi-drop modeAT91C_US_CHMODE EQU (0x3:SHL:14) ;- (DBGU) Channel ModeAT91C_US_CHMODE_NORMAL EQU (0x0:SHL:14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.AT91C_US_CHMODE_AUTO EQU (0x1:SHL:14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.AT91C_US_CHMODE_LOCAL EQU (0x2:SHL:14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.AT91C_US_CHMODE_REMOTE EQU (0x3:SHL:14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.;- -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- AT91C_US_RXRDY EQU (0x1:SHL:0) ;- (DBGU) RXRDY InterruptAT91C_US_TXRDY EQU (0x1:SHL:1) ;- (DBGU) TXRDY InterruptAT91C_US_ENDRX EQU (0x1:SHL:3) ;- (DBGU) End of Receive Transfer InterruptAT91C_US_ENDTX EQU (0x1:SHL:4) ;- (DBGU) End of Transmit InterruptAT91C_US_OVRE EQU (0x1:SHL:5) ;- (DBGU) Overrun InterruptAT91C_US_FRAME EQU (0x1:SHL:6) ;- (DBGU) Framing Error InterruptAT91C_US_PARE EQU (0x1:SHL:7) ;- (DBGU) Parity Error InterruptAT91C_US_TXEMPTY EQU (0x1:SHL:9) ;- (DBGU) TXEMPTY InterruptAT91C_US_TXBUFE EQU (0x1:SHL:11) ;- (DBGU) TXBUFE InterruptAT91C_US_RXBUFF EQU (0x1:SHL:12) ;- (DBGU) RXBUFF InterruptAT91C_US_COMM_TX EQU (0x1:SHL:30) ;- (DBGU) COMM_TX InterruptAT91C_US_COMM_RX EQU (0x1:SHL:31) ;- (DBGU) COMM_RX Interrupt;- -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- ;- -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- ;- -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- ;- -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- AT91C_US_FORCE_NTRST EQU (0x1:SHL:0) ;- (DBGU) Force NTRST in JTAG;- *****************************************************************************;- SOFTWARE API DEFINITION FOR Peripheral Data Controller;- ***************************************************************************** ^ 0 ;- AT91S_PDCPDC_RPR # 4 ;- Receive Pointer RegisterPDC_RCR # 4 ;- Receive Counter RegisterPDC_TPR # 4 ;- Transmit Pointer RegisterPDC_TCR # 4 ;- Transmit Counter RegisterPDC_RNPR # 4 ;- Receive Next Pointer RegisterPDC_RNCR # 4 ;- Receive Next Counter RegisterPDC_TNPR # 4 ;- Transmit Next Pointer RegisterPDC_TNCR # 4 ;- Transmit Next Counter RegisterPDC_PTCR # 4 ;- PDC Transfer Control RegisterPDC_PTSR # 4 ;- PDC Transfer Status Register;- -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- AT91C_PDC_RXTEN EQU (0x1:SHL:0) ;- (PDC) Receiver Transfer EnableAT91C_PDC_RXTDIS EQU (0x1:SHL:1) ;- (PDC) Receiver Transfer DisableAT91C_PDC_TXTEN EQU (0x1:SHL:8) ;- (PDC) Transmitter Transfer EnableAT91C_PDC_TXTDIS EQU (0x1:SHL:9) ;- (PDC) Transmitter Transfer Disable;- -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- ;- *****************************************************************************;- SOFTWARE API DEFINITION FOR Advanced Interrupt Controller;- ***************************************************************************** ^ 0 ;- AT91S_AICAIC_SMR # 128 ;- Source Mode RegisterAIC_SVR # 128 ;- Source Vector RegisterAIC_IVR # 4 ;- IRQ Vector RegisterAIC_FVR # 4 ;- FIQ Vector RegisterAIC_ISR # 4 ;- Interrupt Status RegisterAIC_IPR # 4 ;- Interrupt Pending RegisterAIC_IMR # 4 ;- Interrupt Mask RegisterAIC_CISR # 4 ;- Core Interrupt Status Register # 8 ;- ReservedAIC_IECR # 4 ;- Interrupt Enable Command RegisterAIC_IDCR # 4 ;- Interrupt Disable Command RegisterAIC_ICCR # 4 ;- Interrupt Clear Command RegisterAIC_ISCR # 4 ;- Interrupt Set Command RegisterAIC_EOICR # 4 ;- End of Interrupt Command RegisterAIC_SPU # 4 ;- Spurious Vector RegisterAIC_DCR # 4 ;- Debug Control Register (Protect) # 4 ;- ReservedAIC_FFER # 4 ;- Fast Forcing Enable RegisterAIC_FFDR # 4 ;- Fast Forcing Disable RegisterAIC_FFSR # 4 ;- Fast Forcing Status Register;- -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- AT91C_AIC_PRIOR EQU (0x7:SHL:0) ;- (AIC) Priority LevelAT91C_AIC_PRIOR_LOWEST EQU (0x0) ;- (AIC) Lowest priority levelAT91C_AIC_PRIOR_HIGHEST EQU (0x7) ;- (AIC) Highest priority levelAT91C_AIC_SRCTYPE EQU (0x3:SHL:5) ;- (AIC) Interrupt Source TypeAT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE EQU (0x0:SHL:5) ;- (AIC) Internal Sources Code Label Level SensitiveAT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED EQU (0x1:SHL:5) ;- (AIC) Internal Sources Code Label Edge triggeredAT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL EQU (0x2:SHL:5) ;- (AIC) External Sources Code Label High-level SensitiveAT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE EQU (0x3:SHL:5) ;- (AIC) External Sources Code Label Positive Edge triggered;- -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- AT91C_AIC_NFIQ EQU (0x1:SHL:0) ;- (AIC) NFIQ StatusAT91C_AIC_NIRQ EQU (0x1:SHL:1) ;- (AIC) NIRQ Status;- -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- AT91C_AIC_DCR_PROT EQU (0x1:SHL:0) ;- (AIC) Protection ModeAT91C_AIC_DCR_GMSK EQU (0x1:SHL:1) ;- (AIC) General Mask;- *****************************************************************************;- SOFTWARE API DEFINITION FOR Serial Parallel Interface;- ***************************************************************************** ^ 0 ;- AT91S_SPISPI_CR # 4 ;- Control RegisterSPI_MR # 4 ;- Mode RegisterSPI_RDR # 4 ;- Receive Data RegisterSPI_TDR # 4 ;- Transmit Data RegisterSPI_SR # 4 ;- Status RegisterSPI_IER # 4 ;- Interrupt Enable RegisterSPI_IDR # 4 ;- Interrupt Disable RegisterSPI_IMR # 4 ;- Interrupt Mask Register # 16 ;- ReservedSPI_CSR # 16 ;- Chip Select Register # 192 ;- ReservedSPI_RPR # 4 ;- Receive Pointer RegisterSPI_RCR # 4 ;- Receive Counter RegisterSPI_TPR # 4 ;- Transmit Pointer RegisterSPI_TCR # 4 ;- Transmit Counter RegisterSPI_RNPR # 4 ;- Receive Next Pointer RegisterSPI_RNCR # 4 ;- Receive Next Counter RegisterSPI_TNPR # 4 ;- Transmit Next Pointer RegisterSPI_TNCR # 4 ;- Transmit Next Counter RegisterSPI_PTCR # 4 ;- PDC Transfer Control RegisterSPI_PTSR # 4 ;- PDC Transfer Status Register;- -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- AT91C_SPI_SPIEN EQU (0x1:SHL:0) ;- (SPI) SPI EnableAT91C_SPI_SPIDIS EQU (0x1:SHL:1) ;- (SPI) SPI DisableAT91C_SPI_SWRST EQU (0x1:SHL:7) ;- (SPI) SPI Software reset;- -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- AT91C_SPI_MSTR EQU (0x1:SHL:0) ;- (SPI) Master/Slave ModeAT91C_SPI_PS EQU (0x1:SHL:1) ;- (SPI) Peripheral SelectAT91C_SPI_PS_FIXED EQU (0x0:SHL:1) ;- (SPI) Fixed Peripheral SelectAT91C_SPI_PS_VARIABLE EQU (0x1:SHL:1) ;- (SPI) Variable Peripheral SelectAT91C_SPI_PCSDEC EQU (0x1:SHL:2) ;- (SPI) Chip Select DecodeAT91C_SPI_DIV32 EQU (0x1:SHL:3) ;- (SPI) Clock SelectionAT91C_SPI_MODFDIS EQU (0x1:SHL:4) ;- (SPI) Mode Fault DetectionAT91C_SPI_LLB EQU (0x1:SHL:7) ;- (SPI) Clock SelectionAT91C_SPI_PCS EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip SelectAT91C_SPI_DLYBCS EQU (0xFF:SHL:24) ;- (SPI) Delay Between Chip Selects;- -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- AT91C_SPI_RD EQU (0xFFFF:SHL:0) ;- (SPI) Receive DataAT91C_SPI_RPCS EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select Status;- -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- AT91C_SPI_TD EQU (0xFFFF:SHL:0) ;- (SPI) Transmit DataAT91C_SPI_TPCS EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select Status;- -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- AT91C_SPI_RDRF EQU (0x1:SHL:0) ;- (SPI) Receive Data Register FullAT91C_SPI_TDRE EQU (0x1:SHL:1) ;- (SPI) Transmit Data Register EmptyAT91C_SPI_MODF EQU (0x1:SHL:2) ;- (SPI) Mode Fault ErrorAT91C_SPI_OVRES EQU (0x1:SHL:3) ;- (SPI) Overrun Error StatusAT91C_SPI_SPENDRX EQU (0x1:SHL:4) ;- (SPI) End of Receiver TransferAT91C_SPI_SPENDTX EQU (0x1:SHL:5) ;- (SPI) End of Receiver TransferAT91C_SPI_RXBUFF EQU (0x1:SHL:6) ;- (SPI) RXBUFF InterruptAT91C_SPI_TXBUFE EQU (0x1:SHL:7) ;- (SPI) TXBUFE InterruptAT91C_SPI_SPIENS EQU (0x1:SHL:16) ;- (SPI) Enable Status;- -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- ;- -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- ;- -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- ;- -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- AT91C_SPI_CPOL EQU (0x1:SHL:0) ;- (SPI) Clock PolarityAT91C_SPI_NCPHA EQU (0x1:SHL:1) ;- (SPI) Clock PhaseAT91C_SPI_BITS EQU (0xF:SHL:4) ;- (SPI) Bits Per TransferAT91C_SPI_BITS_8 EQU (0x0:SHL:4) ;- (SPI) 8 Bits Per transferAT91C_SPI_BITS_9 EQU (0x1:SHL:4) ;- (SPI) 9 Bits Per transferAT91C_SPI_BITS_10 EQU (0x2:SHL:4) ;- (SPI) 10 Bits Per transferAT91C_SPI_BITS_11 EQU (0x3:SHL:4) ;- (SPI) 11 Bits Per transferAT91C_SPI_BITS_12 EQU (0x4:SHL:4) ;- (SPI) 12 Bits Per transferAT91C_SPI_BITS_13 EQU (0x5:SHL:4) ;- (SPI) 13 Bits Per transferAT91C_SPI_BITS_14 EQU (0x6:SHL:4) ;- (SPI) 14 Bits Per transferAT91C_SPI_BITS_15 EQU (0x7:SHL:4) ;- (SPI) 15 Bits Per transferAT91C_SPI_BITS_16 EQU (0x8:SHL:4) ;- (SPI) 16 Bits Per transferAT91C_SPI_SCBR EQU (0xFF:SHL:8) ;- (SPI) Serial Clock Baud RateAT91C_SPI_DLYBS EQU (0xFF:SHL:16) ;- (SPI) Serial Clock Baud RateAT91C_SPI_DLYBCT EQU (0xFF:SHL:24) ;- (SPI) Delay Between Consecutive Transfers;- *****************************************************************************;- SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface;- ***************************************************************************** ^ 0 ;- AT91S_SSCSSC_CR # 4 ;- Control RegisterSSC_CMR # 4 ;- Clock Mode Register # 8 ;- ReservedSSC_RCMR # 4 ;- Receive Clock ModeRegisterSSC_RFMR # 4 ;- Receive Frame Mode RegisterSSC_TCMR # 4 ;- Transmit Clock Mode RegisterSSC_TFMR # 4 ;- Transmit Frame Mode RegisterSSC_RHR # 4 ;- Receive Holding RegisterSSC_THR # 4 ;- Transmit Holding Register # 8 ;- ReservedSSC_RSHR # 4 ;- Receive Sync Holding RegisterSSC_TSHR # 4 ;- Transmit Sync Holding RegisterSSC_RC0R # 4 ;- Receive Compare 0 RegisterSSC_RC1R # 4 ;- Receive Compare 1 RegisterSSC_SR # 4 ;- Status RegisterSSC_IER # 4 ;- Interrupt Enable RegisterSSC_IDR # 4 ;- Interrupt Disable RegisterSSC_IMR # 4 ;- Interrupt Mask Register # 176 ;- ReservedSSC_RPR # 4 ;- Receive Pointer RegisterSSC_RCR # 4 ;- Receive Counter RegisterSSC_TPR # 4 ;- Transmit Pointer RegisterSSC_TCR # 4 ;- Transmit Counter RegisterSSC_RNPR # 4 ;- Receive Next Pointer RegisterSSC_RNCR # 4 ;- Receive Next Counter RegisterSSC_TNPR # 4 ;- Transmit Next Pointer RegisterSSC_TNCR # 4 ;- Transmit Next Counter RegisterSSC_PTCR # 4 ;- PDC Transfer Control RegisterSSC_PTSR # 4 ;- PDC Transfer Status Register;- -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- AT91C_SSC_RXEN EQU (0x1:SHL:0) ;- (SSC) Receive EnableAT91C_SSC_RXDIS EQU (0x1:SHL:1) ;- (SSC) Receive Disable⌨️ 快捷键说明
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