📄 at91rm9200.inc
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AT91C_ST_ALMV EQU (0xFFFFF:SHL:0) ;- (ST) Alarm Value Value;- -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register -------- AT91C_ST_CRTV EQU (0xFFFFF:SHL:0) ;- (ST) Current Real-time Value;- *****************************************************************************;- SOFTWARE API DEFINITION FOR Power Management Controler;- ***************************************************************************** ^ 0 ;- AT91S_PMCPMC_SCER # 4 ;- System Clock Enable RegisterPMC_SCDR # 4 ;- System Clock Disable RegisterPMC_SCSR # 4 ;- System Clock Status Register # 4 ;- ReservedPMC_PCER # 4 ;- Peripheral Clock Enable RegisterPMC_PCDR # 4 ;- Peripheral Clock Disable RegisterPMC_PCSR # 4 ;- Peripheral Clock Status Register # 20 ;- ReservedPMC_MCKR # 4 ;- Master Clock Register # 12 ;- ReservedPMC_PCKR # 32 ;- Programmable Clock RegisterPMC_IER # 4 ;- Interrupt Enable RegisterPMC_IDR # 4 ;- Interrupt Disable RegisterPMC_SR # 4 ;- Status RegisterPMC_IMR # 4 ;- Interrupt Mask Register;- -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- AT91C_PMC_PCK EQU (0x1:SHL:0) ;- (PMC) Processor ClockAT91C_PMC_UDP EQU (0x1:SHL:1) ;- (PMC) USB Device Port ClockAT91C_PMC_MCKUDP EQU (0x1:SHL:2) ;- (PMC) USB Device Port Master Clock Automatic Disable on SuspendAT91C_PMC_UHP EQU (0x1:SHL:4) ;- (PMC) USB Host Port ClockAT91C_PMC_PCK0 EQU (0x1:SHL:8) ;- (PMC) Programmable Clock OutputAT91C_PMC_PCK1 EQU (0x1:SHL:9) ;- (PMC) Programmable Clock OutputAT91C_PMC_PCK2 EQU (0x1:SHL:10) ;- (PMC) Programmable Clock OutputAT91C_PMC_PCK3 EQU (0x1:SHL:11) ;- (PMC) Programmable Clock OutputAT91C_PMC_PCK4 EQU (0x1:SHL:12) ;- (PMC) Programmable Clock OutputAT91C_PMC_PCK5 EQU (0x1:SHL:13) ;- (PMC) Programmable Clock OutputAT91C_PMC_PCK6 EQU (0x1:SHL:14) ;- (PMC) Programmable Clock OutputAT91C_PMC_PCK7 EQU (0x1:SHL:15) ;- (PMC) Programmable Clock Output;- -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- ;- -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- ;- -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- AT91C_PMC_CSS EQU (0x3:SHL:0) ;- (PMC) Programmable Clock SelectionAT91C_PMC_CSS_SLOW_CLK EQU (0x0) ;- (PMC) Slow Clock is selectedAT91C_PMC_CSS_MAIN_CLK EQU (0x1) ;- (PMC) Main Clock is selectedAT91C_PMC_CSS_PLLA_CLK EQU (0x2) ;- (PMC) Clock from PLL A is selectedAT91C_PMC_CSS_PLLB_CLK EQU (0x3) ;- (PMC) Clock from PLL B is selectedAT91C_PMC_PRES EQU (0x7:SHL:2) ;- (PMC) Programmable Clock PrescalerAT91C_PMC_PRES_CLK EQU (0x0:SHL:2) ;- (PMC) Selected clockAT91C_PMC_PRES_CLK_2 EQU (0x1:SHL:2) ;- (PMC) Selected clock divided by 2AT91C_PMC_PRES_CLK_4 EQU (0x2:SHL:2) ;- (PMC) Selected clock divided by 4AT91C_PMC_PRES_CLK_8 EQU (0x3:SHL:2) ;- (PMC) Selected clock divided by 8AT91C_PMC_PRES_CLK_16 EQU (0x4:SHL:2) ;- (PMC) Selected clock divided by 16AT91C_PMC_PRES_CLK_32 EQU (0x5:SHL:2) ;- (PMC) Selected clock divided by 32AT91C_PMC_PRES_CLK_64 EQU (0x6:SHL:2) ;- (PMC) Selected clock divided by 64AT91C_PMC_MDIV EQU (0x3:SHL:8) ;- (PMC) Master Clock DivisionAT91C_PMC_MDIV_1 EQU (0x0:SHL:8) ;- (PMC) The master clock and the processor clock are the sameAT91C_PMC_MDIV_2 EQU (0x1:SHL:8) ;- (PMC) The processor clock is twice as fast as the master clockAT91C_PMC_MDIV_3 EQU (0x2:SHL:8) ;- (PMC) The processor clock is three times faster than the master clockAT91C_PMC_MDIV_4 EQU (0x3:SHL:8) ;- (PMC) The processor clock is four times faster than the master clock;- -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- ;- -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- AT91C_PMC_MOSCS EQU (0x1:SHL:0) ;- (PMC) MOSC Status/Enable/Disable/MaskAT91C_PMC_LOCKA EQU (0x1:SHL:1) ;- (PMC) PLL A Status/Enable/Disable/MaskAT91C_PMC_LOCKB EQU (0x1:SHL:2) ;- (PMC) PLL B Status/Enable/Disable/MaskAT91C_PMC_MCKRDY EQU (0x1:SHL:3) ;- (PMC) MCK_RDY Status/Enable/Disable/MaskAT91C_PMC_PCK0RDY EQU (0x1:SHL:8) ;- (PMC) PCK0_RDY Status/Enable/Disable/MaskAT91C_PMC_PCK1RDY EQU (0x1:SHL:9) ;- (PMC) PCK1_RDY Status/Enable/Disable/MaskAT91C_PMC_PCK2RDY EQU (0x1:SHL:10) ;- (PMC) PCK2_RDY Status/Enable/Disable/MaskAT91C_PMC_PCK3RDY EQU (0x1:SHL:11) ;- (PMC) PCK3_RDY Status/Enable/Disable/MaskAT91C_PMC_PCK4RDY EQU (0x1:SHL:12) ;- (PMC) PCK4_RDY Status/Enable/Disable/MaskAT91C_PMC_PCK5RDY EQU (0x1:SHL:13) ;- (PMC) PCK5_RDY Status/Enable/Disable/MaskAT91C_PMC_PCK6RDY EQU (0x1:SHL:14) ;- (PMC) PCK6_RDY Status/Enable/Disable/MaskAT91C_PMC_PCK7RDY EQU (0x1:SHL:15) ;- (PMC) PCK7_RDY Status/Enable/Disable/Mask;- -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- ;- -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- ;- -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- ;- *****************************************************************************;- SOFTWARE API DEFINITION FOR Clock Generator Controler;- ***************************************************************************** ^ 0 ;- AT91S_CKGRCKGR_MOR # 4 ;- Main Oscillator RegisterCKGR_MCFR # 4 ;- Main Clock Frequency RegisterCKGR_PLLAR # 4 ;- PLL A RegisterCKGR_PLLBR # 4 ;- PLL B Register;- -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- AT91C_CKGR_MOSCEN EQU (0x1:SHL:0) ;- (CKGR) Main Oscillator EnableAT91C_CKGR_OSCTEST EQU (0x1:SHL:1) ;- (CKGR) Oscillator TestAT91C_CKGR_OSCOUNT EQU (0xFF:SHL:8) ;- (CKGR) Main Oscillator Start-up Time;- -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- AT91C_CKGR_MAINF EQU (0xFFFF:SHL:0) ;- (CKGR) Main Clock FrequencyAT91C_CKGR_MAINRDY EQU (0x1:SHL:16) ;- (CKGR) Main Clock Ready;- -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- AT91C_CKGR_DIVA EQU (0xFF:SHL:0) ;- (CKGR) Divider SelectedAT91C_CKGR_DIVA_0 EQU (0x0) ;- (CKGR) Divider output is 0AT91C_CKGR_DIVA_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassedAT91C_CKGR_PLLACOUNT EQU (0x3F:SHL:8) ;- (CKGR) PLL A CounterAT91C_CKGR_OUTA EQU (0x3:SHL:14) ;- (CKGR) PLL A Output Frequency RangeAT91C_CKGR_OUTA_0 EQU (0x0:SHL:14) ;- (CKGR) Please refer to the PLLA datasheetAT91C_CKGR_OUTA_1 EQU (0x1:SHL:14) ;- (CKGR) Please refer to the PLLA datasheetAT91C_CKGR_OUTA_2 EQU (0x2:SHL:14) ;- (CKGR) Please refer to the PLLA datasheetAT91C_CKGR_OUTA_3 EQU (0x3:SHL:14) ;- (CKGR) Please refer to the PLLA datasheetAT91C_CKGR_MULA EQU (0x7FF:SHL:16) ;- (CKGR) PLL A MultiplierAT91C_CKGR_SRCA EQU (0x1:SHL:29) ;- (CKGR) PLL A Source;- -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- AT91C_CKGR_DIVB EQU (0xFF:SHL:0) ;- (CKGR) Divider SelectedAT91C_CKGR_DIVB_0 EQU (0x0) ;- (CKGR) Divider output is 0AT91C_CKGR_DIVB_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassedAT91C_CKGR_PLLBCOUNT EQU (0x3F:SHL:8) ;- (CKGR) PLL B CounterAT91C_CKGR_OUTB EQU (0x3:SHL:14) ;- (CKGR) PLL B Output Frequency RangeAT91C_CKGR_OUTB_0 EQU (0x0:SHL:14) ;- (CKGR) Please refer to the PLLB datasheetAT91C_CKGR_OUTB_1 EQU (0x1:SHL:14) ;- (CKGR) Please refer to the PLLB datasheetAT91C_CKGR_OUTB_2 EQU (0x2:SHL:14) ;- (CKGR) Please refer to the PLLB datasheetAT91C_CKGR_OUTB_3 EQU (0x3:SHL:14) ;- (CKGR) Please refer to the PLLB datasheetAT91C_CKGR_MULB EQU (0x7FF:SHL:16) ;- (CKGR) PLL B MultiplierAT91C_CKGR_USB_96M EQU (0x1:SHL:28) ;- (CKGR) Divider for USB PortsAT91C_CKGR_USB_PLL EQU (0x1:SHL:29) ;- (CKGR) PLL Use;- *****************************************************************************;- SOFTWARE API DEFINITION FOR Parallel Input Output Controler;- ***************************************************************************** ^ 0 ;- AT91S_PIOPIO_PER # 4 ;- PIO Enable RegisterPIO_PDR # 4 ;- PIO Disable RegisterPIO_PSR # 4 ;- PIO Status Register # 4 ;- ReservedPIO_OER # 4 ;- Output Enable RegisterPIO_ODR # 4 ;- Output Disable RegisterrPIO_OSR # 4 ;- Output Status Register # 4 ;- ReservedPIO_IFER # 4 ;- Input Filter Enable RegisterPIO_IFDR # 4 ;- Input Filter Disable RegisterPIO_IFSR # 4 ;- Input Filter Status Register # 4 ;- ReservedPIO_SODR # 4 ;- Set Output Data RegisterPIO_CODR # 4 ;- Clear Output Data RegisterPIO_ODSR # 4 ;- Output Data Status RegisterPIO_PDSR # 4 ;- Pin Data Status RegisterPIO_IER # 4 ;- Interrupt Enable RegisterPIO_IDR # 4 ;- Interrupt Disable RegisterPIO_IMR # 4 ;- Interrupt Mask RegisterPIO_ISR # 4 ;- Interrupt Status RegisterPIO_MDER # 4 ;- Multi-driver Enable RegisterPIO_MDDR # 4 ;- Multi-driver Disable RegisterPIO_MDSR # 4 ;- Multi-driver Status Register # 4 ;- ReservedPIO_PPUDR # 4 ;- Pull-up Disable RegisterPIO_PPUER # 4 ;- Pull-up Enable RegisterPIO_PPUSR # 4 ;- Pad Pull-up Status Register # 4 ;- ReservedPIO_ASR # 4 ;- Select A RegisterPIO_BSR # 4 ;- Select B RegisterPIO_ABSR # 4 ;- AB Select Status Register # 36 ;- ReservedPIO_OWER # 4 ;- Output Write Enable RegisterPIO_OWDR # 4 ;- Output Write Disable RegisterPIO_OWSR # 4 ;- Output Write Status Register;- *****************************************************************************;- SOFTWARE API DEFINITION FOR Debug Unit;- ***************************************************************************** ^ 0 ;- AT91S_DBGUDBGU_CR # 4 ;- Control RegisterDBGU_MR # 4 ;- Mode RegisterDBGU_IER # 4 ;- Interrupt Enable RegisterDBGU_IDR # 4 ;- Interrupt Disable RegisterDBGU_IMR # 4 ;- Interrupt Mask RegisterDBGU_CSR # 4 ;- Channel Status RegisterDBGU_RHR # 4 ;- Receiver Holding RegisterDBGU_THR # 4 ;- Transmitter Holding RegisterDBGU_BRGR # 4 ;- Baud Rate Generator Register # 28 ;- ReservedDBGU_C1R # 4 ;- Chip ID1 RegisterDBGU_C2R # 4 ;- Chip ID2 RegisterDBGU_FNTR # 4 ;- Force NTRST Register # 180 ;- ReservedDBGU_RPR # 4 ;- Receive Pointer RegisterDBGU_RCR # 4 ;- Receive Counter RegisterDBGU_TPR # 4 ;- Transmit Pointer RegisterDBGU_TCR # 4 ;- Transmit Counter RegisterDBGU_RNPR # 4 ;- Receive Next Pointer RegisterDBGU_RNCR # 4 ;- Receive Next Counter RegisterDBGU_TNPR # 4 ;- Transmit Next Pointer RegisterDBGU_TNCR # 4 ;- Transmit Next Counter RegisterDBGU_PTCR # 4 ;- PDC Transfer Control RegisterDBGU_PTSR # 4 ;- PDC Transfer Status Register;- -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- AT91C_US_RSTRX EQU (0x1:SHL:2) ;- (DBGU) Reset ReceiverAT91C_US_RSTTX EQU (0x1:SHL:3) ;- (DBGU) Reset TransmitterAT91C_US_RXEN EQU (0x1:SHL:4) ;- (DBGU) Receiver EnableAT91C_US_RXDIS EQU (0x1:SHL:5) ;- (DBGU) Receiver DisableAT91C_US_TXEN EQU (0x1:SHL:6) ;- (DBGU) Transmitter EnableAT91C_US_TXDIS EQU (0x1:SHL:7) ;- (DBGU) Transmitter Disable;- -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- AT91C_US_PAR EQU (0x7:SHL:9) ;- (DBGU) Parity typeAT91C_US_PAR_EVEN EQU (0x0:SHL:9) ;- (DBGU) Even ParityAT91C_US_PAR_ODD EQU (0x1:SHL:9) ;- (DBGU) Odd ParityAT91C_US_PAR_SPACE EQU (0x2:SHL:9) ;- (DBGU) Parity forced to 0 (Space)AT91C_US_PAR_MARK EQU (0x3:SHL:9) ;- (DBGU) Parity forced to 1 (Mark)AT91C_US_PAR_NONE EQU (0x4:SHL:9) ;- (DBGU) No Parity⌨️ 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