📄 at91rm9200_inc.h
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#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers// *****************************************************************************// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface// *****************************************************************************// *** Register offset in AT91S_SSC structure ***#define SSC_CR ( 0) // Control Register#define SSC_CMR ( 4) // Clock Mode Register#define SSC_RCMR (16) // Receive Clock ModeRegister#define SSC_RFMR (20) // Receive Frame Mode Register#define SSC_TCMR (24) // Transmit Clock Mode Register#define SSC_TFMR (28) // Transmit Frame Mode Register#define SSC_RHR (32) // Receive Holding Register#define SSC_THR (36) // Transmit Holding Register#define SSC_RSHR (48) // Receive Sync Holding Register#define SSC_TSHR (52) // Transmit Sync Holding Register#define SSC_RC0R (56) // Receive Compare 0 Register#define SSC_RC1R (60) // Receive Compare 1 Register#define SSC_SR (64) // Status Register#define SSC_IER (68) // Interrupt Enable Register#define SSC_IDR (72) // Interrupt Disable Register#define SSC_IMR (76) // Interrupt Mask Register#define SSC_RPR (256) // Receive Pointer Register#define SSC_RCR (260) // Receive Counter Register#define SSC_TPR (264) // Transmit Pointer Register#define SSC_TCR (268) // Transmit Counter Register#define SSC_RNPR (272) // Receive Next Pointer Register#define SSC_RNCR (276) // Receive Next Counter Register#define SSC_TNPR (280) // Transmit Next Pointer Register#define SSC_TNCR (284) // Transmit Next Counter Register#define SSC_PTCR (288) // PDC Transfer Control Register#define SSC_PTSR (292) // PDC Transfer Status Register// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- #define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- #define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection#define AT91C_SSC_STTOUT (0x1 << 15) // (SSC) Receive/Transmit Start Output Selection#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- #define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- // -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- #define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- #define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- // -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- // -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- // *****************************************************************************// SOFTWARE API DEFINITION FOR Usart// *****************************************************************************// *** Register offset in AT91S_USART structure ***#define US_CR ( 0) // Control Register#define US_MR ( 4) // Mode Register#define US_IER ( 8) // Interrupt Enable Register#define US_IDR (12) // Interrupt Disable Register#define US_IMR (16) // Interrupt Mask Register#define US_CSR (20) // Channel Status Register#define US_RHR (24) // Receiver Holding Register#define US_THR (28) // Transmitter Holding Register#define US_BRGR (32) // Baud Rate Generator Register#define US_RTOR (36) // Receiver Time-out Register#define US_TTGR (40) // Transmitter Time-guard Register#define US_FIDI (64) // FI_DI_Ratio Register#define US_NER (68) // Nb Errors Register#define US_XXR (72) // XON_XOFF Register#define US_IF (76) // IRDA_FILTER Register#define US_RPR (256) // Receive Pointer Register#define US_RCR (260) // Receive Counter Register#define US_TPR (264) // Transmit Pointer Register#define US_TCR (268) // Transmit Counter Register#define US_RNPR (272) // Receive Next Pointer Register#define US_RNCR (276) // Receive Next Counter Register#define US_TNPR (280) // Transmit Next Pointer Register#define US_TNCR (284) // Transmit Next Counter Register#define US_PTCR (288) // PDC Transfer Control Register#define US_PTSR (292) // PDC Transfer Status Register// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- #define AT91C_US_RSTSTA (0x1 << 8) // (USART) Reset Status Bits#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- #define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- #define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break⌨️ 快捷键说明
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