📄 at91rm9200_inc.h
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// -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register -------- #define AT91C_ST_PIV (0xFFFF << 0) // (ST) Watchdog Timer Restart// -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register -------- #define AT91C_ST_WDV (0xFFFF << 0) // (ST) Watchdog Timer Restart#define AT91C_ST_RSTEN (0x1 << 16) // (ST) Reset Enable#define AT91C_ST_EXTEN (0x1 << 17) // (ST) External Signal Assertion Enable// -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register -------- #define AT91C_ST_RTPRES (0xFFFF << 0) // (ST) Real-time Timer Prescaler Value// -------- ST_SR : (ST Offset: 0x10) System Timer Status Register -------- #define AT91C_ST_PITS (0x1 << 0) // (ST) Period Interval Timer Interrupt#define AT91C_ST_WDOVF (0x1 << 1) // (ST) Watchdog Overflow#define AT91C_ST_RTTINC (0x1 << 2) // (ST) Real-time Timer Increment#define AT91C_ST_ALMS (0x1 << 3) // (ST) Alarm Status// -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register -------- // -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register -------- // -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register -------- // -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register -------- #define AT91C_ST_ALMV (0xFFFFF << 0) // (ST) Alarm Value Value// -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register -------- #define AT91C_ST_CRTV (0xFFFFF << 0) // (ST) Current Real-time Value// *****************************************************************************// SOFTWARE API DEFINITION FOR Power Management Controler// *****************************************************************************// *** Register offset in AT91S_PMC structure ***#define PMC_SCER ( 0) // System Clock Enable Register#define PMC_SCDR ( 4) // System Clock Disable Register#define PMC_SCSR ( 8) // System Clock Status Register#define PMC_PCER (16) // Peripheral Clock Enable Register#define PMC_PCDR (20) // Peripheral Clock Disable Register#define PMC_PCSR (24) // Peripheral Clock Status Register#define PMC_MCKR (48) // Master Clock Register#define PMC_PCKR (64) // Programmable Clock Register#define PMC_IER (96) // Interrupt Enable Register#define PMC_IDR (100) // Interrupt Disable Register#define PMC_SR (104) // Status Register#define PMC_IMR (108) // Interrupt Mask Register// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- #define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock#define AT91C_PMC_UDP (0x1 << 1) // (PMC) USB Device Port Clock#define AT91C_PMC_MCKUDP (0x1 << 2) // (PMC) USB Device Port Master Clock Automatic Disable on Suspend#define AT91C_PMC_UHP (0x1 << 4) // (PMC) USB Host Port Clock#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output#define AT91C_PMC_PCK4 (0x1 << 12) // (PMC) Programmable Clock Output#define AT91C_PMC_PCK5 (0x1 << 13) // (PMC) Programmable Clock Output#define AT91C_PMC_PCK6 (0x1 << 14) // (PMC) Programmable Clock Output#define AT91C_PMC_PCK7 (0x1 << 15) // (PMC) Programmable Clock Output// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- // -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- // -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- #define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected#define AT91C_PMC_CSS_PLLA_CLK (0x2) // (PMC) Clock from PLL A is selected#define AT91C_PMC_CSS_PLLB_CLK (0x3) // (PMC) Clock from PLL B is selected#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64#define AT91C_PMC_MDIV (0x3 << 8) // (PMC) Master Clock Division#define AT91C_PMC_MDIV_1 (0x0 << 8) // (PMC) The master clock and the processor clock are the same#define AT91C_PMC_MDIV_2 (0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock#define AT91C_PMC_MDIV_3 (0x2 << 8) // (PMC) The processor clock is three times faster than the master clock#define AT91C_PMC_MDIV_4 (0x3 << 8) // (PMC) The processor clock is four times faster than the master clock// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- // -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- #define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask#define AT91C_PMC_LOCKA (0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask#define AT91C_PMC_LOCKB (0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask#define AT91C_PMC_PCK4RDY (0x1 << 12) // (PMC) PCK4_RDY Status/Enable/Disable/Mask#define AT91C_PMC_PCK5RDY (0x1 << 13) // (PMC) PCK5_RDY Status/Enable/Disable/Mask#define AT91C_PMC_PCK6RDY (0x1 << 14) // (PMC) PCK6_RDY Status/Enable/Disable/Mask#define AT91C_PMC_PCK7RDY (0x1 << 15) // (PMC) PCK7_RDY Status/Enable/Disable/Mask// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- // -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- // -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- // *****************************************************************************// SOFTWARE API DEFINITION FOR Clock Generator Controler// *****************************************************************************// *** Register offset in AT91S_CKGR structure ***#define CKGR_MOR ( 0) // Main Oscillator Register#define CKGR_MCFR ( 4) // Main Clock Frequency Register#define CKGR_PLLAR ( 8) // PLL A Register#define CKGR_PLLBR (12) // PLL B Register// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- #define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable#define AT91C_CKGR_OSCTEST (0x1 << 1) // (CKGR) Oscillator Test#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- #define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- #define AT91C_CKGR_DIVA (0xFF << 0) // (CKGR) Divider Selected#define AT91C_CKGR_DIVA_0 (0x0) // (CKGR) Divider output is 0#define AT91C_CKGR_DIVA_BYPASS (0x1) // (CKGR) Divider is bypassed#define AT91C_CKGR_PLLACOUNT (0x3F << 8) // (CKGR) PLL A Counter#define AT91C_CKGR_OUTA (0x3 << 14) // (CKGR) PLL A Output Frequency Range#define AT91C_CKGR_OUTA_0 (0x0 << 14) // (CKGR) Please refer to the PLLA datasheet#define AT91C_CKGR_OUTA_1 (0x1 << 14) // (CKGR) Please refer to the PLLA datasheet#define AT91C_CKGR_OUTA_2 (0x2 << 14) // (CKGR) Please refer to the PLLA datasheet#define AT91C_CKGR_OUTA_3 (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet#define AT91C_CKGR_MULA (0x7FF << 16) // (CKGR) PLL A Multiplier#define AT91C_CKGR_SRCA (0x1 << 29) // (CKGR) PLL A Source// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- #define AT91C_CKGR_DIVB (0xFF << 0) // (CKGR) Divider Selected#define AT91C_CKGR_DIVB_0 (0x0) // (CKGR) Divider output is 0#define AT91C_CKGR_DIVB_BYPASS (0x1) // (CKGR) Divider is bypassed#define AT91C_CKGR_PLLBCOUNT (0x3F << 8) // (CKGR) PLL B Counter#define AT91C_CKGR_OUTB (0x3 << 14) // (CKGR) PLL B Output Frequency Range#define AT91C_CKGR_OUTB_0 (0x0 << 14) // (CKGR) Please refer to the PLLB datasheet#define AT91C_CKGR_OUTB_1 (0x1 << 14) // (CKGR) Please refer to the PLLB datasheet#define AT91C_CKGR_OUTB_2 (0x2 << 14) // (CKGR) Please refer to the PLLB datasheet#define AT91C_CKGR_OUTB_3 (0x3 << 14) // (CKGR) Please refer to the PLLB datasheet#define AT91C_CKGR_MULB (0x7FF << 16) // (CKGR) PLL B Multiplier#define AT91C_CKGR_USB_96M (0x1 << 28) // (CKGR) Divider for USB Ports#define AT91C_CKGR_USB_PLL (0x1 << 29) // (CKGR) PLL Use// *****************************************************************************// SOFTWARE API DEFINITION FOR Parallel Input Output Controler// *****************************************************************************// *** Register offset in AT91S_PIO structure ***#define PIO_PER ( 0) // PIO Enable Register#define PIO_PDR ( 4) // PIO Disable Register#define PIO_PSR ( 8) // PIO Status Register#define PIO_OER (16) // Output Enable Register#define PIO_ODR (20) // Output Disable Registerr#define PIO_OSR (24) // Output Status Register#define PIO_IFER (32) // Input Filter Enable Register#define PIO_IFDR (36) // Input Filter Disable Register#define PIO_IFSR (40) // Input Filter Status Register#define PIO_SODR (48) // Set Output Data Register#define PIO_CODR (52) // Clear Output Data Register#define PIO_ODSR (56) // Output Data Status Register#define PIO_PDSR (60) // Pin Data Status Register#define PIO_IER (64) // Interrupt Enable Register#define PIO_IDR (68) // Interrupt Disable Register#define PIO_IMR (72) // Interrupt Mask Register#define PIO_ISR (76) // Interrupt Status Register#define PIO_MDER (80) // Multi-driver Enable Register#define PIO_MDDR (84) // Multi-driver Disable Register#define PIO_MDSR (88) // Multi-driver Status Register#define PIO_PPUDR (96) // Pull-up Disable Register#define PIO_PPUER (100) // Pull-up Enable Register#define PIO_PPUSR (104) // Pad Pull-up Status Register#define PIO_ASR (112) // Select A Register#define PIO_BSR (116) // Select B Register#define PIO_ABSR (120) // AB Select Status Register#define PIO_OWER (160) // Output Write Enable Register#define PIO_OWDR (164) // Output Write Disable Register#define PIO_OWSR (168) // Output Write Status Register// *****************************************************************************// SOFTWARE API DEFINITION FOR Debug Unit// *****************************************************************************// *** Register offset in AT91S_DBGU structure ***#define DBGU_CR ( 0) // Control Register#define DBGU_MR ( 4) // Mode Register#define DBGU_IER ( 8) // Interrupt Enable Register#define DBGU_IDR (12) // Interrupt Disable Register#define DBGU_IMR (16) // Interrupt Mask Register#define DBGU_CSR (20) // Channel Status Register#define DBGU_RHR (24) // Receiver Holding Register#define DBGU_THR (28) // Transmitter Holding Register#define DBGU_BRGR (32) // Baud Rate Generator Register#define DBGU_C1R (64) // Chip ID1 Register#define DBGU_C2R (68) // Chip ID2 Register#define DBGU_FNTR (72) // Force NTRST Register⌨️ 快捷键说明
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