proc-xscale.s

ARM8008光盘linux-kernel

/*
 *  linux/arch/arm/mm/proc-xscale.S
 *
 *  Author:	Nicolas Pitre
 *  Created:	November 2000
 *  Copyright:	(C) 2000, 2001 MontaVista Software Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * MMU functions for the Intel XScale CPUs
 *
 * 2001 Aug 21:	
 *	some contributions by Brett Gaines <[e-mail]>
 *	Copyright 2001 by Intel Corp.
 *
 * 2001 Sep 08:
 *	Completely revisited, many important fixes
 *	Nicolas Pitre <[e-mail]>
 */

#include <linux/config.h>
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/constants.h>
#include <asm/procinfo.h>
#include <asm/hardware.h>
#include <asm/proc/pgtable.h>

/*
 * Some knobs for cache allocation policy.
 * Allocate on write may or may not be beneficial depending on the memory
 * usage pattern of your main application.  Write through cache is definitely
 * a performance loss in most cases, but might be used for special purposes.
 */
#define PMD_CACHE_WRITE_ALLOCATE 1
#define PTE_CACHE_WRITE_ALLOCATE 1
#define CACHE_WRITE_THROUGH 0

/*
 * There are errata that say that dirty status bits in the cache may get
 * corrupted. The workaround significantly affects performance, and the bug
 * _might_ just not be that visible or critical to you, so it is configurable.
 * Let's hope a future core revision will tell us this was only a bad dream.
 * But in the mean time the risk and tradeoff is yours to decide....
 */
#ifdef CONFIG_XSCALE_CACHE_ERRATA
#undef CACHE_WRITE_THROUGH
#define CACHE_WRITE_THROUGH 1
#endif

/* 
 * This is the maximum size of an area which will be flushed.  If the area
 * is larger than this, then we flush the whole cache
 */
#define MAX_AREA_SIZE	32768

/*
 * the cache line size of the I and D cache
 */
#define CACHELINESIZE	32

/*
 * the size of the data cache
 */
#define CACHESIZE	32768

/*
 * and the page size
 */
#define PAGESIZE	4096

/*
 * Virtual address used to allocate the cache when flushed
 *
 * This must be an address range which is _never_ used.  It should 
 * apparently have a mapping in the corresponding page table for 
 * compatibility with future CPUs that _could_ require it.  For instance we
 * don't care.
 *
 * This must be aligned on a 2*CACHESIZE boundary.  The code selects one of
 * the 2 areas in alternance each time the clean_d_cache macro is used.
 * Without this the XScale core exhibits cache eviction problems and no one
 * knows why.  
 *
 * Reminder: the vector table is located at 0xffff0000-0xffff0fff.
 */
#define CLEAN_ADDR	0xfffe0000

/*
 * This macro is used to wait for a CP15 write and is needed
 * when we have to ensure that the last operation to the co-pro
 * was completed before continuing with operation.
 */
	.macro	cpwait, rd
	mrc	p15, 0, \rd, c2, c0, 0		@ arbitrary read of cp15
	mov	\rd, \rd			@ wait for completion
	sub 	pc, pc, #4			@ flush instruction pipeline
	.endm	

	.macro	cpwait_ret, lr, rd
	mrc	p15, 0, \rd, c2, c0, 0		@ arbitrary read of cp15
	sub	pc, \lr, \rd, LSR #32		@ wait for completion and
						@ flush instruction pipeline
	.endm

#if !CACHE_WRITE_THROUGH

/*
 * This macro cleans the entire dcache using line allocate.
 * The main loop has been unrolled to reduce loop overhead.
 * rd and rs are two scratch registers.
 */
	.macro  clean_d_cache, rd, rs
	ldr	\rs, =clean_addr
	ldr	\rd, [\rs]
	eor	\rd, \rd, #CACHESIZE
	str	\rd, [\rs]
	add	\rs, \rd, #CACHESIZE
1:	mcr	p15, 0, \rd, c7, c2, 5		@ allocate D cache line
	add	\rd, \rd, #CACHELINESIZE
	mcr	p15, 0, \rd, c7, c2, 5		@ allocate D cache line
	add	\rd, \rd, #CACHELINESIZE
	mcr	p15, 0, \rd, c7, c2, 5		@ allocate D cache line
	add	\rd, \rd, #CACHELINESIZE
	mcr	p15, 0, \rd, c7, c2, 5		@ allocate D cache line
	add	\rd, \rd, #CACHELINESIZE
	teq	\rd, \rs
	bne	1b
	.endm

	.macro	clean_d_line,	rd
	mcr	p15, 0, \rd, c7, c10, 1
	.endm

	.data
clean_addr:	.word	CLEAN_ADDR

#else

/*
 * If cache is write-through, there is no need to clean it.
 * Simply invalidating will do.
 */

	.macro  clean_d_cache, rd, rs
	mcr	p15, 0, \rd, c7, c6, 0
	.endm

	/* let's try to skip this needless operations at least within loops */
	.macro	clean_d_line,	rd
	.endm

#endif

	.text

/*
 * cpu_xscale_data_abort()
 *
 * obtain information about current aborted instruction.
 * Note: we read user space.  This means we might cause a data
 * abort here if the I-TLB and D-TLB aren't seeing the same
 * picture.  Unfortunately, this does happen.  We live with it.
 *
 *  r2 = address of aborted instruction
 *  r3 = cpsr
 *
 * Returns:
 *  r0 = address of abort
 *  r1 != 0 if writing
 *  r3 = FSR
 *  r4 = corrupted
 */
	.align	5
ENTRY(cpu_xscale_data_abort)
	mrc	p15, 0, r3, c5, c0, 0		@ get FSR
	mrc	p15, 0, r0, c6, c0, 0		@ get FAR
	ldr	r1, [r2]			@ read aborted instruction
	and	r3, r3, #255
	tst	r1, r1, lsr #21			@ C = bit 20
	sbc	r1, r1, r1			@ r1 = C - 1
	mov	pc, lr

/*
 * cpu_xscale_check_bugs()
 */
ENTRY(cpu_xscale_check_bugs)
	mrs	ip, cpsr
	bic	ip, ip, #F_BIT
	msr	cpsr, ip
	mov	pc, lr

#ifndef CONFIG_XSCALE_CACHE_ERRATA
/*
 * cpu_xscale_proc_init()
 *
 * Nothing too exciting at the moment
 */
ENTRY(cpu_xscale_proc_init)
	mov	pc, lr
#else
/*
 * We enable the cache here, but we make sure all the status bits for dirty
 * lines are cleared as well (see PXA250 erratum #120).
 */
ENTRY(cpu_xscale_proc_init)
	@ enable data cache
	ldr	r0, cr_p
	ldmia	r0, {r1, r2}
	orr	r1, r1, #0x4
	orr	r2, r2, #0x4
	stmia	r0, {r1, r2}
	mcr	p15, 0, r1, c1, c0, 0
	cpwait	r0

	@ invalidate data cache
	mcr	p15, 0, r0, c7, c6, 0

	@ fill main cache with write-through lines
	bic	r0, pc, #0x1f
	add	r1, r0, #CACHESIZE
1:	ldr	r2, [r0], #32
	cmp	r0, r1
	bne	1b

	@ enable test feature to force all fills to the mini-cache
	mov	r1, #0x8
	mcr	p15, 0, r1, c15, c15, 3

	@ fill mini-cache with write-through lines (2kbytes, 64 lines)
	add	r1, r0, #2048
2:	ldr	r2, [r0], #32
	cmp	r0, r1
	bne	2b

	@ disable test feature to force all fills to the mini-cache
	mov	r1, #0x0
	mcr	p15, 0, r1, c15, c15, 3

	@ invalidate data cache again
	mcr	p15, 0, r1, c7, c6, 0
	mov	pc, lr

cr_p:	.long	SYMBOL_NAME(cr_alignment)
#endif

/*
 * cpu_xscale_proc_fin()
 */
ENTRY(cpu_xscale_proc_fin)
	str	lr, [sp, #-4]!
	mov	r0, #F_BIT|I_BIT|SVC_MODE
	msr	cpsr_c, r0
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1800			@ ...IZ...........
	bic	r0, r0, #0x0006			@ .............CA.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	bl	cpu_xscale_cache_clean_invalidate_all	@ clean caches
	ldr	pc, [sp], #4

/*
 * cpu_xscale_reset(loc)
 *
 * Perform a soft reset of the system.  Put the CPU into the
 * same state as it would be if it had been reset, and branch
 * to what would be the reset vector.
 *
 * loc: location to jump to for soft reset
 */
	.align	5
ENTRY(cpu_xscale_reset)
	mov	r1, #F_BIT|I_BIT|SVC_MODE
	msr	cpsr_c, r1			@ reset CPSR
	mrc	p15, 0, r1, c1, c0, 0		@ ctrl register
	bic	r1, r1, #0x0086			@ ........B....CA.
	bic	r1, r1, #0x1900			@ ...IZ..S........
	mcr	p15, 0, r1, c1, c0, 0		@ ctrl register
	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches & BTB
	bic	r1, r1, #0x0001			@ ...............M
	mcr	p15, 0, r1, c1, c0, 0		@ ctrl register
	@ CAUTION: MMU turned off from this point. We count on the pipeline 
	@ already containing those two last instructions to survive.
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
	mov	pc, r0

/*
 * cpu_xscale_do_idle(type)
 *
 * Cause the processor to idle
 *
 * type: 
 *   0 = slow idle
 *   1 = fast idle
 *   2 = switch to slow processor clock
 *   3 = switch to fast processor clock
 *
 * For now we do nothing but go to idle mode for every case
 *
 * XScale supports clock switching, but using idle mode support
 * allows external hardware to react to system state changes.
 */
	.align	5

ENTRY(cpu_xscale_do_idle)
	mov	r0, #1
	mcr	p14, 0, r0, c7, c0, 0		@ Go to IDLE
	mov	pc, lr

/* ================================= CACHE ================================ */

/*
 * cpu_xscale_cache_clean_invalidate_all (void)
 *
 * clean and invalidate all cache lines
 *
 * Note:
 *  1. We should preserve r0 at all times.
 *  2. Even if this function implies cache "invalidation" by its name,
 *     we don't need to actually use explicit invalidation operations
 *     since the goal is to discard all valid references from the cache
 *     and the cleaning of it already has that effect.
 *  3. Because of 2 above and the fact that kernel space memory is always
 *     coherent across task switches there is no need to worry about
 *     inconsistencies due to interrupts, ence no irq disabling.
 */
	.align	5
ENTRY(cpu_xscale_cache_clean_invalidate_all)
	mov	r2, #1
cpu_xscale_cache_clean_invalidate_all_r2:
	clean_d_cache r0, r1
	teq	r2, #0
	mcrne	p15, 0, ip, c7, c5, 0		@ Invalidate I cache & BTB
	mcr	p15, 0, ip, c7, c10, 4		@ Drain Write (& Fill) Buffer
	mov	pc, lr

/*
 * cpu_xscale_cache_clean_invalidate_range(start, end, flags)
 *
 * clean and invalidate all cache lines associated with this area of memory
 *
 * start: Area start address
 * end:   Area end address
 * flags: nonzero for I cache as well
 */
	.align	5
ENTRY(cpu_xscale_cache_clean_invalidate_range)
	bic	r0, r0, #CACHELINESIZE - 1	@ round down to cache line
	sub	r3, r1, r0
	cmp	r3, #MAX_AREA_SIZE
	bhi	cpu_xscale_cache_clean_invalidate_all_r2
1:	clean_d_line r0				@ Clean D cache line
	mcr	p15, 0, r0, c7, c6, 1		@ Invalidate D cache line
	add	r0, r0, #CACHELINESIZE
	cmp	r0, r1
	blo	1b
	teq	r2, #0
	mcr	p15, 0, ip, c7, c10, 4		@ Drain Write (& Fill) Buffer
	moveq	pc, lr
	sub	r0, r0, r3
1:	mcr	p15, 0, r0, c7, c5, 1		@ Invalidate I cache line
	add	r0, r0, #CACHELINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, ip, c7, c5, 6		@ Invalidate BTB
	mov	pc, lr

/*
 * cpu_xscale_flush_ram_page(page)
 *
 * clean all cache lines associated with this memory page
 *
 * page: page to clean
 */
	.align	5
ENTRY(cpu_xscale_flush_ram_page)
#if !CACHE_WRITE_THROUGH
	mov	r1, #PAGESIZE
1:	mcr	p15, 0, r0, c7, c10, 1		@ Clean D cache line
	add	r0, r0, #CACHELINESIZE
	mcr	p15, 0, r0, c7, c10, 1		@ Clean D cache line
	add	r0, r0, #CACHELINESIZE
	subs	r1, r1, #2 * CACHELINESIZE
	bne	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ Drain Write (& Fill) Buffer
	mov	pc, lr

/* ================================ D-CACHE =============================== */

/*
 * cpu_xscale_dcache_invalidate_range(start, end)
 *
 * throw away all D-cached data in specified region without an obligation
 * to write them back.  Note however that on XScale we must clean all
 * entries also due to hardware errata (80200 A0 & A1 only).
 *
 * start: virtual start address
 * end:   virtual end address
 */
	.align	5
ENTRY(cpu_xscale_dcache_invalidate_range)
	mrc	p15, 0, r2, c0, c0, 0		@ Read part no.
	eor	r2, r2, #0x69000000
	eor	r2, r2, #0x00052000		@ 80200 XX part no.
	bics	r2, r2, #0x1			@ Clear LSB in revision field
	moveq	r2, #0
	beq	cpu_xscale_cache_clean_invalidate_range	@ An 80200 A0 or A1

	tst	r0, #CACHELINESIZE - 1
	mcrne	p15, 0, r0, c7, c10, 1		@ Clean D cache line
	tst	r1, #CACHELINESIZE - 1
	mcrne	p15, 0, r1, c7, c10, 1		@ Clean D cache line
	bic	r0, r0, #CACHELINESIZE - 1	@ round down to cache line
1:	mcr	p15, 0, r0, c7, c6, 1		@ Invalidate D cache line
	add	r0, r0, #CACHELINESIZE
	cmp	r0, r1
	blo	1b
	mov	pc, lr

/*
 * cpu_xscale_dcache_clean_range(start, end)
 *
 * For the specified virtual address range, ensure that all caches contain
 * clean data, such that peripheral accesses to the physical RAM fetch
 * correct data.
 *
 * start: virtual start address
 * end:   virtual end address
 */
	.align	5
ENTRY(cpu_xscale_dcache_clean_range)
#if !CACHE_WRITE_THROUGH
	bic	r0, r0, #CACHELINESIZE - 1
	sub	r2, r1, r0
	cmp	r2, #MAX_AREA_SIZE
	movhi	r2, #0
	bhi	cpu_xscale_cache_clean_invalidate_all_r2

1:	mcr	p15, 0, r0, c7, c10, 1		@ Clean D cache line
	add	r0, r0, #CACHELINESIZE
	mcr	p15, 0, r0, c7, c10, 1		@ Clean D cache line
	add	r0, r0, #CACHELINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ Drain Write (& Fill) Buffer
	mov	pc, lr

/*
 * cpu_xscale_clean_dcache_page(page)
 *
 * Cleans a single page of dcache so that if we have any future aliased
 * mappings, they will be consistent at the time that they are created.
 *
 * Note:
 *  1. we don't need to flush the write buffer in this case. [really? -Nico]
 *  2. we don't invalidate the entries since when we write the page
 *     out to disk, the entries may get reloaded into the cache.
 */
	.align	5
ENTRY(cpu_xscale_dcache_clean_page)
#if !CACHE_WRITE_THROUGH
	mov	r1, #PAGESIZE
1:	mcr	p15, 0, r0, c7, c10, 1		@ Clean D cache line
	add	r0, r0, #CACHELINESIZE
	mcr	p15, 0, r0, c7, c10, 1		@ Clean D cache line
	add	r0, r0, #CACHELINESIZE
	mcr	p15, 0, r0, c7, c10, 1		@ Clean D cache line
	add	r0, r0, #CACHELINESIZE
	mcr	p15, 0, r0, c7, c10, 1		@ Clean D cache line
	add	r0, r0, #CACHELINESIZE
	subs	r1, r1, #4 * CACHELINESIZE
	bne	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ Drain Write (& Fill) Buffer
	mov	pc, lr

/*
 * cpu_xscale_dcache_clean_entry(addr)
 *
 * Clean the specified entry of any caches such that the MMU
 * translation fetches will obtain correct data.
 *
 * addr: cache-unaligned virtual address
 */
	.align	5
ENTRY(cpu_xscale_dcache_clean_entry)
	mcr	p15, 0, r0, c7, c10, 1		@ Clean D cache line
	mcr	p15, 0, ip, c7, c10, 4		@ Drain Write (& Fill) Buffer
	mov	pc, lr

/* ================================ I-CACHE =============================== */

/*
 * cpu_xscale_icache_invalidate_range(start, end)
 *
 * invalidate a range of virtual addresses from the Icache
 *
 * start: virtual start address
 * end:   virtual end address
 *
 * Note: This is vaguely defined as supposed to bring the dcache and the 
 *       icache in sync by the way this function is used.
 */
	.align	5
ENTRY(cpu_xscale_icache_invalidate_range)
	bic	r0, r0, #CACHELINESIZE - 1
1:	clean_d_line r0				@ Clean D cache line
	mcr	p15, 0, r0, c7, c5, 1		@ Invalidate I cache line
	add	r0, r0, #CACHELINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, ip, c7, c5, 6		@ Invalidate BTB
	mcr	p15, 0, ip, c7, c10, 4		@ Drain Write (& Fill) Buffer