ww_rass.lst

国内某测温系统信号处理处理板的代码

__text_start:
__start:
    00BB E5CF      LDI	R28,0x5F
    00BC E0D2      LDI	R29,2
    00BD BFCD      OUT	0x3D,R28
    00BE BFDE      OUT	0x3E,R29
    00BF 51C0      SUBI	R28,0x10
    00C0 40D0      SBCI	R29,0
    00C1 EA0A      LDI	R16,0xAA
    00C2 8308      STD	Y+0,R16
    00C3 2400      CLR	R0
    00C4 E6E5      LDI	R30,0x65
    00C5 E0F0      LDI	R31,0
    00C6 E010      LDI	R17,0
    00C7 37EB      CPI	R30,0x7B
    00C8 07F1      CPC	R31,R17
    00C9 F011      BEQ	0x00CC
    00CA 9201      ST	R0,Z+
    00CB CFFB      RJMP	0x00C7
    00CC 8300      STD	Z+0,R16
    00CD E7E0      LDI	R30,0x70
    00CE E0F1      LDI	R31,1
    00CF E6A0      LDI	R26,0x60
    00D0 E0B0      LDI	R27,0
    00D1 E011      LDI	R17,1
    00D2 37E5      CPI	R30,0x75
    00D3 07F1      CPC	R31,R17
    00D4 F021      BEQ	0x00D9
    00D5 95C8      LPM
    00D6 9631      ADIW	R30,1
    00D7 920D      ST	R0,X+
    00D8 CFF9      RJMP	0x00D2
    00D9 D11C      RCALL	_main
_exit:
    00DA CFFF      RJMP	_exit
FILE: E:\任务\RASS\rass_soft\init_8515.c
(0001) //ICC-AVR application builder : 2006-12-8 14:54:31
(0002) // Target : M8515
(0003) // Crystal: 7.3728Mhz
(0004) 
(0005) #include "config.h"
(0006) 
(0007) void port_init(void)
(0008) {
(0009)  PORTA = 0x00;
_port_init:
    00DB 2422      CLR	R2
    00DC BA2B      OUT	0x1B,R2
(0010)  DDRA  = 0xFF;
    00DD EF8F      LDI	R24,0xFF
    00DE BB8A      OUT	0x1A,R24
(0011)  PORTB = 0x00;
    00DF BA28      OUT	0x18,R2
(0012)  DDRB  = 0x40;
    00E0 E480      LDI	R24,0x40
    00E1 BB87      OUT	0x17,R24
(0013)  PORTC = 0x38;
    00E2 E388      LDI	R24,0x38
    00E3 BB85      OUT	0x15,R24
(0014)  DDRC  = 0xFF;
    00E4 EF8F      LDI	R24,0xFF
    00E5 BB84      OUT	0x14,R24
(0015)  PORTD = 0x03;
    00E6 E083      LDI	R24,3
    00E7 BB82      OUT	0x12,R24
(0016)  DDRD  = 0x00; 
    00E8 BA21      OUT	0x11,R2
(0017)  PORTE = 0x07;
    00E9 E087      LDI	R24,7
    00EA B987      OUT	0x07,R24
(0018)  DDRE  = 0x00; 
    00EB B826      OUT	0x06,R2
    00EC 9508      RET
(0019) }
(0020) 
(0021) //TIMER1 initialize - prescale:1024
(0022) // WGM: 0) Normal, TOP=0xFFFF
(0023) // desired value: 2Sec
(0024) // actual value:  2.000Sec (0.0%)
(0025) void timer1_init(void)
(0026) {
(0027)  TCCR1B = 0x00; //stop
_timer1_init:
    00ED 2422      CLR	R2
    00EE BC2E      OUT	0x2E,R2
(0028)  TCNT1H = 0xC7; //setup
    00EF EC87      LDI	R24,0xC7
    00F0 BD8D      OUT	0x2D,R24
(0029)  TCNT1L = 0xC1;
    00F1 EC81      LDI	R24,0xC1
    00F2 BD8C      OUT	0x2C,R24
(0030)  OCR1AH = 0x38;
    00F3 E388      LDI	R24,0x38
    00F4 BD8B      OUT	0x2B,R24
(0031)  OCR1AL = 0x3F;
    00F5 E38F      LDI	R24,0x3F
    00F6 BD8A      OUT	0x2A,R24
(0032)  OCR1BH = 0x38;
    00F7 E388      LDI	R24,0x38
    00F8 BD89      OUT	0x29,R24
(0033)  OCR1BL = 0x3F;
    00F9 E38F      LDI	R24,0x3F
    00FA BD88      OUT	0x28,R24
(0034)  TCCR1A = 0x00;
    00FB BC2F      OUT	0x2F,R2
    00FC 9508      RET
(0035)  //TCCR1B = 0x05; //start Timer
(0036) }
(0037) 
(0038) 
(0039) //UART0 initialize
(0040) // desired baud rate: 19200
(0041) // actual: baud rate:19200 (0.0%)
(0042) void uart0_init(void)
(0043) {
(0044)  UCSRB = 0x00; //disable while setting baud rate
_uart0_init:
    00FD 2422      CLR	R2
    00FE B82A      OUT	0x0A,R2
(0045)  UCSRA = 0x00;
    00FF B82B      OUT	0x0B,R2
(0046)  UCSRC = BIT(URSEL) | 0x36;
    0100 EB86      LDI	R24,0xB6
    0101 BD80      OUT	0x20,R24
(0047)  UBRRL = 0x17; //set baud rate lo
    0102 E187      LDI	R24,0x17
    0103 B989      OUT	0x09,R24
(0048)  UBRRH = 0x00; //set baud rate hi
    0104 BC20      OUT	0x20,R2
(0049)  UCSRB = 0xD8;
    0105 ED88      LDI	R24,0xD8
    0106 B98A      OUT	0x0A,R24
    0107 9508      RET
(0050) }
(0051) 
(0052) 
(0053) 
(0054) //Comparator initialize
(0055) // trigger on: Rising output edge
(0056) void comparator_init(void)
(0057) {
(0058)  ACSR = ACSR & 0xF7; //ensure interrupt is off before changing
_comparator_init:
    0108 B188      IN	R24,0x08
    0109 7F87      ANDI	R24,0xF7
    010A B988      OUT	0x08,R24
(0059)  ACSR = 0x0B;
    010B E08B      LDI	R24,0xB
    010C B988      OUT	0x08,R24
    010D 9508      RET
_timer1_ovf_isr:
    010E D2D7      RCALL	push_lset
FILE: E:\任务\RASS\rass_soft\interrupt.c
(0001) #include "config.h"
(0002) 
(0003) extern unsigned char dp2rass[5];
(0004) extern unsigned char rass2dp;
(0005) extern unsigned int test_freq;
(0006) extern unsigned char rxed_flag;
(0007) extern unsigned int seed;
(0008) extern unsigned char timer1;
(0009) extern unsigned int TCNT1_H;
(0010) extern unsigned int TCNT1_L;
(0011) extern unsigned int D15_0;
(0012) 
(0013) 
(0014) //#pragma interrupt_handler timer1_ovf_isr:7
(0015) void timer1_ovf_isr(void)
(0016) {
(0017) 	//在这里改变频率
(0018)  timer1=1;
    010F E081      LDI	R24,1
    0110 93800065  STS	timer1,R24
(0019)  TCNT1H = TCNT1_H; //reload counter high value
    0112 90200068  LDS	R2,TCNT1_H
    0114 90300069  LDS	R3,TCNT1_L
    0116 BC2D      OUT	0x2D,R2
(0020)  TCNT1L = TCNT1_L; //reload counter low value
    0117 90200069  LDS	R2,TCNT1_L
    0119 9030006A  LDS	R3,Fl
    011B BC2C      OUT	0x2C,R2
(0021)  ml2035(D15_0,1);
    011C E021      LDI	R18,1
    011D E030      LDI	R19,0
    011E 91000066  LDS	R16,D15_0
    0120 91100067  LDS	R17,D15_0+1
    0122 D169      RCALL	_ml2035
(0022)  SEI();
    0123 9478      BSET	7
    0124 D2D8      RCALL	pop_lset
    0125 9518      RETI
_uart0_rx_isr:
  mid                  --> R16
    0126 922A      ST	R2,-Y
    0127 923A      ST	R3,-Y
    0128 930A      ST	R16,-Y
    0129 938A      ST	R24,-Y
    012A 939A      ST	R25,-Y
    012B 93EA      ST	R30,-Y
    012C 93FA      ST	R31,-Y
    012D B62F      IN	R2,0x3F
    012E 922A      ST	R2,-Y
(0023) }
(0024) 
(0025) 
(0026) 
(0027) //#pragma interrupt_handler uart0_rx_isr:10
(0028) void uart0_rx_isr(void)
(0029) {
(0030)  //uart has received a character in UDR
(0031)  static int rxnum=0;
(0032)  unsigned char mid;
(0033)  mid=UDR;
    012F B10C      IN	R16,0x0C
(0034)  
(0035)  
(0036)  if(!(mid&0x01))//判断是命令还是数据请求,是请求，则
    0130 FD00      SBRC	R16,0
    0131 C006      RJMP	0x0138
(0037) 	 {
(0038) 	 	rxed_flag=1;
    0132 E081      LDI	R24,1
    0133 93800064  STS	rxed_flag,R24
(0039) 	 	dp2rass[0]=mid;
    0135 93000076  STS	dp2rass,R16
(0040) 		return;
    0137 C028      RJMP	0x0160
(0041) 	 }
(0042) 			           
(0043)  dp2rass[rxnum++]=mid;
    0138 90200060  LDS	R2,rxnum
    013A 90300061  LDS	R3,rxnum+1
    013C 01C1      MOVW	R24,R2
    013D 9601      ADIW	R24,1
    013E 93900061  STS	rxnum+1,R25
    0140 93800060  STS	rxnum,R24
    0142 E786      LDI	R24,0x76
    0143 E090      LDI	R25,0
    0144 01F1      MOVW	R30,R2
    0145 0FE8      ADD	R30,R24
    0146 1FF9      ADC	R31,R25
    0147 8300      STD	Z+0,R16
(0044)  PORTC ^=1<<pc0;
    0148 E081      LDI	R24,1
    0149 B225      IN	R2,0x15
    014A 2628      EOR	R2,R24
    014B BA25      OUT	0x15,R2
(0045)  if(rxnum>4)
    014C E084      LDI	R24,4
    014D E090      LDI	R25,0
    014E 90200060  LDS	R2,rxnum
    0150 90300061  LDS	R3,rxnum+1
    0152 1582      CP	R24,R2
    0153 0593      CPC	R25,R3
    0154 F454      BGE	0x015F
(0046)  	{
(0047)  		rxnum=0;
    0155 2422      CLR	R2
    0156 2433      CLR	R3
    0157 92300061  STS	rxnum+1,R3
    0159 92200060  STS	rxnum,R2
(0048)  		PORTC &=~(1<<pc0);
    015B 98A8      CBI	0x15,0
(0049)  		rxed_flag=1;
    015C E081      LDI	R24,1
    015D 93800064  STS	rxed_flag,R24
(0050)  	}
(0051)  SEI();
    015F 9478      BSET	7
    0160 9029      LD	R2,Y+
    0161 BE2F      OUT	0x3F,R2
    0162 91F9      LD	R31,Y+
    0163 91E9      LD	R30,Y+
    0164 9199      LD	R25,Y+
    0165 9189      LD	R24,Y+
    0166 9109      LD	R16,Y+
    0167 9039      LD	R3,Y+
    0168 9029      LD	R2,Y+
    0169 9518      RETI
_uart0_tx_isr:
    016A D27B      RCALL	push_lset
(0052) }
(0053) 
(0054) 
(0055) 
(0056) //#pragma interrupt_handler uart0_tx_isr:12
(0057) void uart0_tx_isr(void)
(0058) {
(0059)  //character has been transmitted
(0060)  //use pc0 to show transmitter over
(0061)  PORTC |=1<<pc1;
    016B 9AA9      SBI	0x15,1
(0062)  delay_us(100);
    016C E604      LDI	R16,0x64
    016D D158      RCALL	_delay_us
(0063)  PORTC &=~(1<<pc1);
    016E 98A9      CBI	0x15,1
(0064)  SEI();
    016F 9478      BSET	7
    0170 D28C      RCALL	pop_lset
    0171 9518      RETI
_ana_comp_isr:
  dert_freq            --> R20
  dert_time            --> R20
  ana_com              --> Y+0
    0172 922A      ST	R2,-Y
    0173 923A      ST	R3,-Y
    0174 924A      ST	R4,-Y
    0175 925A      ST	R5,-Y
    0176 930A      ST	R16,-Y
    0177 931A      ST	R17,-Y
    0178 932A      ST	R18,-Y
    0179 933A      ST	R19,-Y
    017A 938A      ST	R24,-Y
    017B 939A      ST	R25,-Y
    017C 93EA      ST	R30,-Y
    017D 93FA      ST	R31,-Y
    017E B62F      IN	R2,0x3F
    017F 922A      ST	R2,-Y
    0180 D24C      RCALL	push_gset2
    0181 9724      SBIW	R28,4
(0065) }
(0066) 
(0067) 
(0068) //#pragma interrupt_handler ana_comp_isr:13
(0069) void ana_comp_isr(void)
(0070) {
(0071)  //analog comparator compare event
(0072)  rass2dp=0;
    0182 2422      CLR	R2
    0183 92200063  STS	rass2dp,R2
(0073)  PORTC ^=1<<pc2;
    0185 E084      LDI	R24,4
    0186 B225      IN	R2,0x15
    0187 2628      EOR	R2,R24
    0188 BA25      OUT	0x15,R2
(0074)  if(ana_freq)
    0189 C05B      RJMP	0x01E5
(0075)  	{
(0076) 	  //unsigned int test_freq;
(0077)     unsigned int ana_com[2];
(0078)     unsigned int dert_time;
(0079)     static unsigned char ana_num=0;
(0080)     unsigned int dert_freq;
(0081)     
(0082)  		ana_com[ana_num++]=(TCNT1H<<8)+TCNT1L;
    018A 90200062  LDS	R2,ana_num
    018C 2433      CLR	R3
    018D 2D82      MOV	R24,R2
    018E 5F8F      SUBI	R24,0xFF
    018F 93800062  STS	ana_num,R24
    0191 E002      LDI	R16,2
    0192 E010      LDI	R17,0
    0193 0191      MOVW	R18,R2
    0194 D220      RCALL	empy16s
    0195 01F8      MOVW	R30,R16
    0196 01CE      MOVW	R24,R28
    0197 0FE8      ADD	R30,R24
    0198 1FF9      ADC	R31,R25
    0199 B42C      IN	R2,0x2C
    019A B43D      IN	R3,0x2D
    019B 8231      STD	Z+1,R3
    019C 8220      STD	Z+0,R2
(0083)  		if(ana_num>1)
    019D E081      LDI	R24,1
    019E 90200062  LDS	R2,ana_num
    01A0 1582      CP	R24,R2
    01A1 F008      BCS	0x01A3
    01A2 C042      RJMP	0x01E5
(0084)  			{
(0085)  				ana_num=0;
    01A3 2422      CLR	R2
    01A4 92200062  STS	ana_num,R2
(0086)  				if(ana_com[0]<ana_com[1])
    01A6 802A      LDD	R2,Y+2
    01A7 803B      LDD	R3,Y+3
    01A8 8048      LDD	R4,Y+0
    01A9 8059      LDD	R5,Y+1
    01AA 1442      CP	R4,R2
    01AB 0453      CPC	R5,R3
    01AC F420      BCC	0x01B1
(0087)  					dert_time=ana_com[1]-ana_com[0];
    01AD 01A1      MOVW	R20,R2
    01AE 1944      SUB	R20,R4
    01AF 0955      SBC	R21,R5
    01B0 C008      RJMP	0x01B9
(0088)  				else
(0089)  					dert_time=ana_com[1]+0xffff-ana_com[0];
    01B1 8028      LDD	R2,Y+0
    01B2 8039      LDD	R3,Y+1
    01B3 814A      LDD	R20,Y+2
    01B4 815B      LDD	R21,Y+3
    01B5 5041      SUBI	R20,1
    01B6 4050      SBCI	R21,0
    01B7 1942      SUB	R20,R2
    01B8 0953      SBC	R21,R3
(0090)  				test_freq =7200/(dert_time+1);
    01B9 019A      MOVW	R18,R20
    01BA 5F2F      SUBI	R18,0xFF
    01BB 4F3F      SBCI	R19,0xFF