event.c

基于ADI 公司的blackfin芯片的通用中断框架程序

#include "event.h"

#include "..\core_event\core_event.h"

#include "..\sys_event\sys_event.h"


static void idle_isr(void)
{
	while(1)
	{
	    asm("raise 6;");
	    
	    asm("[--sp] = reti;");
	    
		asm("idle;");
	}
}


EXTERN void nmi_isr(void);

EXTERN void exception_isr(void);

EXTERN void hardware_error_isr(void);

EXTERN void core_timer_isr(void);

EXTERN void evt7_isr(void);

EXTERN void evt8_isr(void);

EXTERN void evt9_isr(void);

EXTERN void evt10_isr(void);

EXTERN void evt11_isr(void);

EXTERN void evt12_isr(void);

EXTERN void evt13_isr(void);

EXTERN void evt_software1_isr(void);

EXTERN void evt_software2_isr(void);


/* Default System Interrupt Handler */

EXTERN void hk_idle(void);

EXTERN void hk_pll(void);

EXTERN void hk_dma_err(void);

EXTERN void hk_iport_err(void);

EXTERN void hk_rtc(void);

EXTERN void hk_dma0(void);

EXTERN void hk_dma3(void);

EXTERN void hk_dma4(void);

EXTERN void hk_dma5(void);

EXTERN void hk_dma6(void);

EXTERN void hk_twi(void);

EXTERN void hk_dma7(void);

EXTERN void hk_dma8(void);

EXTERN void hk_dma9(void);

EXTERN void hk_dma10(void);

EXTERN void hk_dma11(void);

EXTERN void hk_canrx(void);

EXTERN void hk_cantx(void);

EXTERN void hk_dma1(void);

EXTERN void hk_dma2(void);

EXTERN void hk_tmr0(void);

EXTERN void hk_tmr1(void);

EXTERN void hk_tmr2(void);

EXTERN void hk_tmr3(void);

EXTERN void hk_tmr4(void);

EXTERN void hk_tmr5(void);

EXTERN void hk_tmr6(void);

EXTERN void hk_tmr7(void);

EXTERN void hk_portf(void);

EXTERN void hk_portg(void);

EXTERN void hk_mdma0(void);

EXTERN void hk_mdma1(void);

EXTERN void hk_wtdtmr(void);



void (* const ivg_isr[16])(void) = 
{
	NULL,					// Emulation
	NULL,					// Reset
	&nmi_isr,				// NMI
	&exception_isr, 		// Exception
	NULL,					// Reserved
	&hardware_error_isr,	// Hardware Error
	&core_timer_isr,		// Core Timer
	&evt7_isr,				// IVG7
	&evt8_isr,				// IVG8
	&evt9_isr,				// IVG9
	&evt10_isr, 			// IVG10
	&evt11_isr, 			// IVG11
	&evt12_isr, 			// IVG12
	&evt13_isr, 			// IVG13
	&idle_isr,				// Software Interrupt 1
	&idle_isr				// Software Interrupt 2
};



void (*sys_callback[32])(void) = 
{
	&hk_pll,		// PLL Interrupt
	&hk_dma_err,	// DMA Error, DMARx Block Interrupt, DMARx Overflow Error Interrupt
	&hk_iport_err,	// CAN/MAC/SPORTx/PPI/SPI/UARTx Error Interrupt
	&hk_rtc,		// RTC Interrupt
	&hk_dma0,		// DMA0 Interrupt(PPI)
	&hk_dma3,		// DMA3 Interrupt(SPORT0 Rx)
	&hk_dma4,		// DMA4 Interrupt(SPORT0 Tx)
	&hk_dma5,		// DMA5 Interrupt(SPORT1 Rx)
	&hk_dma6,		// DMA6 Interrupt(SPORT1 Tx)
	&hk_twi,		// TWI Interrupt
	&hk_dma7,		// DMA7 Interrupt(SPI)
	&hk_dma8,		// DMA8 Interrupt(UART0 Rx)
	&hk_dma9,		// DMA9 Interrupt(UART0 Tx)
	&hk_dma10,		// DMA10 Interrupt(UART1 Rx)
	&hk_dma11,		// DMA11 Interrupt(UART1 Tx)
	&hk_canrx,		// CAN Rx Interrupt
	&hk_cantx,		// CAN Tx Interrupt
	&hk_dma1,		// DMA1(MAC Rx), Port H Interrupt A Interrupt
	&hk_dma2,		// DMA2(MAC Tx), Port H Interrupt B Interrupt
	&hk_tmr0,		// Timer0 Interrupt
	&hk_tmr1,		// Timer1 Interrupt
	&hk_tmr2,		// Timer2 Interrupt
	&hk_tmr3,		// Timer3 Interrupt
	&hk_tmr4,		// Timer4 Interrupt
	&hk_tmr5,		// Timer5 Interrupt
	&hk_tmr6,		// Timer6 Interrupt
	&hk_tmr7,		// Timer7 Interrupt
	&hk_portf,		// Port F, G Interrupr A Interrupt
	&hk_portg,		// Port G Interrupt B Interrupt
	&hk_mdma0,		// MDMA0 Interrupt
	&hk_mdma1,		// MDMA1 Interrupt
	&hk_wtdtmr		// Software Watchdog Timer, Port F Interrupt B Interrupt
};


void reg_sys_intrv(HINTR handler, unsigned handler_type)
{
	ASSERT(handler_type < 32);
	
	sys_callback[handler_type] = handler;
}


void unreg_sys_intrv(unsigned handler_type)
{
	ASSERT(handler_type < 32);
	
	sys_callback[handler_type] = &hk_idle;
}


static unsigned imask_tbl[MAX_TEMP_IMASK];

static int imask_tbl_index = -1;

#define IMASK	*(volatile unsigned long*)0xffe02104


void enable_intr(unsigned event_id)
{	
	ASSERT(imask_tbl_index < MAX_TEMP_IMASK);
	
	imask_tbl[++imask_tbl_index] = IMASK;
	
	IMASK |= event_id;
}


void disable_intr(unsigned event_id)
{
	ASSERT(imask_tbl_index < MAX_TEMP_IMASK);
	
	imask_tbl[++imask_tbl_index] = IMASK;
	
	event_id = ~event_id;
	
	IMASK &= event_id;
}


void restore_imask(void)
{
	ASSERT(imask_tbl_index >= 0);
	
	IMASK = imask_tbl[imask_tbl_index--];
}


// assistant operation for core events

// exception and hardware interrupt handler

HINTR g_user_exception_handler = NULL;


void add_user_exception_handler(HINTR handler)
{
    g_user_exception_handler = handler;
}


void cancel_user_exception_handler(void)
{
    g_user_exception_handler = NULL;
}



HINTR g_user_hardware_error_handler = NULL;


void add_user_hardware_error_handler(HINTR handler)
{
    g_user_hardware_error_handler = handler;
}


void cancel_user_hardware_error_handler(void)
{
    g_user_hardware_error_handler = NULL;
}


// core timer event handler

#include <stdio.h>


typedef struct CoreTimerConfig
{
    void(*handler)(const ID*);
    
    unsigned long timer_count;
    
    unsigned long ticks;
    
}CORE_TIMER_CONFIG;


CORE_TIMER_CONFIG g_user_core_timer_handlers[MAX_CORE_TIMER_EVENTS_NUMBER] = { };


int g_nTimerEvents = 0;


ID add_core_timer_event(void(*handler)(const ID*), unsigned long timer_count)
{
    int i;
    
    if(g_nTimerEvents == MAX_CORE_TIMER_EVENTS_NUMBER)
    {
        puts("The number of core timer events exceeded the max limitation!");
        
        return -1;
    }
    
    for(i=0; i<MAX_CORE_TIMER_EVENTS_NUMBER; i++)
    {
        if(g_user_core_timer_handlers[g_nTimerEvents].handler == NULL)
        {
            g_user_core_timer_handlers[g_nTimerEvents].handler = handler;
    
            g_user_core_timer_handlers[g_nTimerEvents].timer_count = timer_count;
            
            g_user_core_timer_handlers[g_nTimerEvents].ticks = timer_count;
        }
    }
    
    i = g_nTimerEvents++;
    
    return i;
}


void remove_core_timer_event(ID timer_id)
{
    if(g_nTimerEvents == 0)
    {
        puts("No core timer event to be removed!");
        
        return;
    }
    
    g_nTimerEvents--;
    
    ASSERT(timer_id >= 0 && timer_id < MAX_CORE_TIMER_EVENTS_NUMBER);
    
    g_user_core_timer_handlers[timer_id].handler = NULL;
}


//! core timer control register
#define TCNTL	*(volatile unsigned long*)0xffe03000


//! core timer count register
#define TCOUNT	*(volatile unsigned long*)0xffe0300c


//! core timer period register
#define TPERIOD	*(volatile unsigned long*)0xffe03004


//! core timer scale register
#define TSCALE	*(volatile unsigned long*)0xffe03008



void init_timer(void)
{
    TCNTL = 1;		// enable core timer
    
    TCOUNT = CORE_TIMER_TICK;
    
    TPERIOD = CORE_TIMER_TICK;
    
    TSCALE = 0;
}


void start_core_timer(void)
{
    TCNTL = 7;
}


void stop_core_timer(void)
{
    TCNTL = 0;
}



void core_timer_handler(void)
{
    int i;
    
    if(g_nTimerEvents == 0)
    	return;
    
    for(i=0; i<MAX_CORE_TIMER_EVENTS_NUMBER; i++)
    {
        if(g_user_core_timer_handlers[i].handler != NULL)
        {
            if(g_user_core_timer_handlers[i].ticks == 0 || --g_user_core_timer_handlers[i].ticks == 0)
            {
            	g_user_core_timer_handlers[i].ticks = g_user_core_timer_handlers[i].timer_count;
            	
            	(*g_user_core_timer_handlers[i].handler)(&i);
            
              // OPTIONAL:   remove_core_timer_event(i);
            }
        }
    }
}