valuetbl.h

主要用于液晶电视解码,内置51单片机,全部代码用C编写,编译环境为KEILC

  {BK1_DC_GPO_FRP_TRAN, SET_FRP_TRAN},
  {BK1_DD_GPO_STH_STT, SET_STH_START},
  {BK1_DE_GPO_STH_WIDTH, SET_STH_WIDTH},
  {BK1_DF_GPO_OEH_STT, SET_OEH_START},
  {BK1_E0_GPO_OEH_WIDTH, SET_OEH_WIDTH},
  {BK1_E1_GPO_OEV_STT, SET_OEV_START},
  {BK1_E2_GPO_OEV_WIDTH, SET_OEV_WIDTH},
  {BK1_E3_GPO_CKV_STT, SET_CKV_START},
  {BK1_E4_GPO_CKV_STT2, SET_CKV_START2},
  {BK1_E5_GPO_CKV_WIDTH, SET_CKV_WIDTH},
  {BK1_E6_GPO_STV_LN_TH, SET_STV_LINE_TH},
  {BK1_E7_GPO_STV_STT, SET_STV_START},
  {BK1_E8_GPO_STV_WIDTH, SET_STV_WIDTH},
  {BK1_E9_GPO_OEV2_STT, SET_OEV2_START},
  {BK1_EA_GPO_OEV3_STT, SET_OEV3_START},
  {BK1_EB_HSTT_DLY_L, SET_H_ST_DLY_L},
  {BK1_EC_HSTT_DLY_H, SET_H_ST_DLY_H},
  {BK1_ED_CLK_DLY_SYNC_OUT, SET_CLK_DLY_SYNC_OUT},
  {BK1_EE_GPO_CKV_END2, SET_CKV_END2},
  {BK1_EF_Q1H_SETTING, SET_Q1H},

#if (( PANEL_TYPE==PanelPVI10_AT)||(PANEL_TYPE==PanelPVI08_AT))        // For PVI10" Panel
  {BK1_D3_LN_EXTR_CNT_LMT, 0x00},
  {BK1_D4_LN_EXTR_SET1_H, 0x00},
  {BK1_D5_LN_EXTR_SET1_L, 0x00},
  {BK1_D6_LN_EXTR_SET2_H, 0x00},
  {BK1_D7_LN_EXTR_SET2_L, 0x00},
  {BK1_D8_EXTR_STT_LN1, 0x00},
  {BK1_D9_EXTR_END_LN1, 0x00},
  {BK1_DA_EXTR_STT_LN2, 0x00},
  {BK1_DB_EXTR_END_LN2, 0x13},
  {BK1_CB_IPOL_SET1, 0x08},
  {BK1_EF_Q1H_SETTING, 0x00},
#endif

#if PANEL_ANALOG_TCON
//VCOM SETTING
 // {BK1_43_BVOM_DC, SET_BVOM_DC},
  //{BK1_44_BVOM_OUT, SET_BVOM_OUT},
// Power setting
  {BK1_46, 0x00},
  {BK1_47, 0x00},
  {BK1_48, 0x00},
  {BK1_49, 0x0F},
  {BK1_4A, 0x00},
  {BK1_4B, 0x40},
  {BK1_4C, 0x30},
  {BK1_4D, 0x55},
  {BK1_4E, 0x58},
  {BK1_4F, 0x00},
// DAC output setting
  {BK1_A9_PD_VDAC, 0x00},
  {BK1_AA_VDAC_ADJ1, SET_VDAC_ADJ1},
  {BK1_AB_VDAC_ADJ2, SET_VDAC_ADJ2},
#else
  {BK1_45, 0x01},
  {BK1_4A, 0xF1},
  {BK1_4B, 0x5F},
  {BK1_4C, 0x51},
#endif

  {_END_OF_TBL_, 0x00}
};

RegUnitType code tInitializeVFE[] =
{
  {BK0_00_REGBK, REG_BANK2_VD},		// select register bank VFE

  {BK2_15_FPGA_CTRL, 0x82}, // FPGA_CTRL
  {BK2_17_FSC_SEL, 0xF9},

#if( ENABLE_SECAM )
  {BK2_19_MVDET_EN, 0xC2},
#endif

  {BK2_1E_REG_DSP_EN, 0x80},	// For SECAM input

  {BK2_23_APLL_TRANGE, 0x80},
//  {BK2_26_APL_K1_NORMAL, 0x20},
//  {BK2_27_APL_K2_NORMAL, 0x08},

  {BK2_28_APL_K1_VCR,0x20},
  {BK2_3C_HV_CTRL1,0x1A},
  {BK2_4A_AGC_LOWTH, 0xFF}, // AGC_LOWTH 20051117.MH.Liao for AGC
  {BK2_4E_BK_WINDOW1, 0x25}, // BK_WINDOW1
  {BK2_5A_BRST_UNKNOW_TH, 0x2F}, // BRST_UNKNOWN_TH
  {BK2_62, 0x10}, // AP_SYNTH2REAGC 20051117.MH.Liao for AGC redo  {BK2_2F_BLACK_SEL, 0x24},

  {BK2_67_WP_REDO, 0x17},	// 20051208  0x07}, // 20051004 David.Shen

  {BK2_6A_VCR_DETECT1,0x91},

    {BK2_6F, 0x81}, // 20051123.Eric.Lin: Using old SW reset, DE by pass
    //{BK2_6F, 0x83}, // 20051123.Eric.Lin: Using old SW reset, DE by pass! Because thar it will cause vtotal unstable
                    // 20060123.Daniel Test!! The setting equal to Paulo

  {BK2_72, 0x74}, // HV_SLC_CTRL
  //{BK2_73_INI_CTRL2,0xF0},
  {BK2_76_656_CTRL1, 0x04},	// For Mode1, enable 656 mode (20050722)
  {BK2_77, 0x01},


  //{BK2_7D_NOISE_MLINE, 0x01}, // NOISE_MLINE
  {BK2_7E_656_CTRL2, 0x80}, // 20051128.Eric:656_CTRL2


  {BK2_8F_FSC_TABLE, 0x19},

  {BK2_94_SPL_SPD_CTRL1, 0x0C}, // 20051230.KC: Lock H sync speed when no signal

  {BK2_9D_DPL_NSPL_HIGH, _656_PLL_VALUE},
  {BK2_9E_DPL_NSPL_LOW, 0x20},

  {BK2_96_EDGES_NOISY_TH, 0x60}, // 20051202.Eric.Lin: For Noise Mag


  {BK2_A0_DPL_K1_FORCE, 0x1A}, // 20060424. Michael
  {BK2_A1_DPL_K2_FORCE, 0x35}, // 20060424. Michael

  {BK2_A2_DPL_K1_NOISY, 0x2B}, // 20060216: Daniel.Wu
  {BK2_A3_DPL_K2_NOISY, 0x40}, // 20060216: Daniel.Wu
  {BK2_AB, 0x02},

  {BK2_B2, 0x99}, // 20051207.KC: 0x19 -> 0x99 For line lock
  {BK2_B9, 0x3F}, // 20051202.Eric.Lin: For DSP_18
  {BK2_BA, 0x3F}, // 20051202.Eric.Lin: For DSP_18

#if (!ENABLE_VD_DSP )
  #if( !ENABLE_SW_FILED )
  {BK2_BB, 0x06}, // Using COMB' VSync,Filed
  #endif
#endif

  {BK0_00_REGBK, REG_BANK_SCALER},		// select register bank scaler
  {_END_OF_TBL_, 0x00}
};


RegUnitType code tInitializeVCE[] =
{
    {BK0_00_REGBK, REG_BANK3_COMB},		// select register bank VCF
    // select demodulation mode 0 (11h[5] = 1b'0)
    {BK3_11_COMBCFGB, 0x20},
    {BK3_12, 0x00}, // Don't use comb snow
    {BK3_13, INIT_MSVD_COMB_YGAIN},//0xA0}, // YGAIN
    {BK3_14, INIT_MSVD_COMB_CbGAIN}, // CBGAIN
    {BK3_15, INIT_MSVD_COMB_CrGAIN}, // CRGAIN

    {BK3_16, 0x66},
    {BK3_17, 0x66},

    {BK3_1C_CTRLSWCH, 0xB3},//0xF3},//0xB3},     // bit7: H sync from AFEC
                        // bit6: V sync from AFEC
                        // bit5: Black level from AFEC
                        // bit4: Demodulation degree from afec
                        // bit[1:0] NTSC/PAL decision
                        //  01: force NTSC
                        //  10: force PAL
                        //  Other: auto detect

    {BK3_21_COMB2DCFGB,0xEF},//0xE7},
    {BK3_22_COMB2DCFGC,0x83},//0x8F},
    {BK3_23_COMB2DCFGD,0x40},//0x60},
    {BK3_24_TH2DHOR,0x20},//0x60},
    {BK3_25_TLRNLUMA,0x18},//0x30},
    {BK3_26_THCRMAERR,0x10},//0x30},
    {BK3_27_THHORCHKV, 0x00},//0x10}, // 20051115.Daniel.Shen
    {BK3_48_BSTLVL_TH,0x00},

#if 1
    {BK3_63_REG_CTST, INIT_MSVD_COMB_CONTRAST}, // VD Contrast
    {BK3_64_REG_BRHT, INIT_MSVD_COMB_BRIGHTNESS}, // VD Brightness
    {BK3_65_REG_SAT, INIT_MSVD_COMB_SATURATION}, // VD Saturation
#endif

    {BK3_66_SENSCTST,0x80},
    {BK3_60_IMGCTRL,0xD0},

	// For SECAM setting
#if( ENABLE_SECAM )
    {BK3_A1_SCM_IDSET1, 0x00},
    {BK3_A2, 0x98},
    {BK3_A4_LINE_START_A, 0x1B},
    {BK3_A5_LINE_START_B, 0x54},
    {BK3_A7_LINE_LENGTH, 0xF0},//0x66},
    {BK3_A8_ACT_MULTIPLE, 0x01},//0x02},
    {BK3_A9, 0x60},//0x00},
    {BK3_AA, 0x21},// 20060313.CJ.Hung: Detect Secam threshold
    {BK3_AE, 0x88}, // 20060405.Daniel

    {BK3_B0, 0xFD},
    {BK3_B1, 0x03},
    {BK3_B2, 0x87},
    {BK3_B3, 0x0B},
    {BK3_B4, 0xF5},
    {BK3_B5, 0x86},

    {BK0_00_REGBK, REG_BANK2_VD}, // Bank VD
    {BK2_19_MVDET_EN, 0xC2},
#endif

    {BK0_00_REGBK, REG_BANK_SCALER},		// select register bank scaler
    {_END_OF_TBL_, 0x00}
};


#if (CCFL_FUNCTION)
RegUnitType code tInitializeCCFL[] =
{
   	{BK0_00_REGBK, REG_BANK4_LVDS_CCFL},		// select register bank VCF

   	{BK4_6B, 0x80},
   	{BK4_9A, 0xCF},

	#if CCFL_BURST_MODE
   	{BK4_6E, 0x0D},
	#else
   	{BK4_6E, 0x0C},
	#endif


   	{BK4_72, 0xF5},
   	{BK4_73, 0xE9},
   	{BK4_74, 0x32},
   	{BK4_75, 0x22},

   	{BK4_78, 0x12},
   	{BK4_79, 0x00},
   	{BK4_7A, 0xFF},
   	{BK4_7B, 0x38},

//   {BK4_86, 0x01},
//   {BK4_85, 0x3C},

	{BK4_8A, 0x01},
   	{BK4_89, 0x16},

#if CCFL_BURST_MODE
	{BK4_8F, 0x00},
   	{BK4_8E, 0xAE},
#endif

	{BK4_91, 0x00},
   	{BK4_90, 0xAE}, //0xAE},//

#if PANEL_ANALOG_TCON
	{BK4_AB, 0x13},
#else
	{BK4_AB, 0x93},
#endif

   //	{BK4_AC, 0x81},

#if LED_BACKLIGHT //100K freq
   	{BK4_86, 0x00},
   	{BK4_85, 0xB4},//0x64
#else
   	{BK4_86, 0x01},
   	{BK4_85, 0x3C},
#endif

#if ENABLE_MCU_USE_INTERNAL_CLOCK
	{BK4_B0, 0x93},  //for 27Mhz
   	{BK4_B1, 0x01},
#else
	{BK4_B0, 0xB3},
   	{BK4_B1, 0x00},
#endif
   	{BK4_B2, 0x0A},
   	{BK4_6B, 0x00},

  	{BK0_00_REGBK, REG_BANK_SCALER},		// select register bank scaler
  	{_END_OF_TBL_, 0x00}
};
#endif