valuetbl.h

主要用于液晶电视解码,内置51单片机,全部代码用C编写,编译环境为KEILC

#if VGA_ENABLE
// analog port
RegUnitType code tProgVGAPort[] =
{
    {BK0_00_REGBK, REG_BANK1_ADC_ACE_MCU},
    {BK1_0A, 0x10}, // clamp placement
    //{BK1_0B, 0x05}, // clamp duration
    {BK1_0B, 0x08}, // clamp duration
    {BK1_0C_GCTRL, 0x02}, // coast polarity as high
    {BK1_14_SOG_LVL, 0x00}, // Disable Middle clamp of Red/Blue Channel
//  {BK1_2F, 0x20}, // ADC Mux
//  {BK1_35, 0x10}, // set SOG trigger level

    {BK0_00_REGBK, REG_BANK_SCALER},

#if SOG_ENABLE
    {BK0_02_ISELECT, _BIT7|0x60},
#else
    {BK0_02_ISELECT, _BIT7|0x20},
#endif

    {BK0_03_IPCTRL2, _BIT3},
    {BK0_04_ISCTRL, _BIT1|_BIT0},
    {BK0_10_COCTRL1, 0x01}, // enable ADC coast
//  {BK0_11, 0x00}, // enable coast window start
//  {BK0_12, 0x00}, // enable coast window end

    {_END_OF_TBL_, 0x00}
};
#endif

RegUnitType code tProgMsAvPort[] =
{
    {BK0_00_REGBK, REG_BANK_SCALER},
    {BK0_02_ISELECT, _BIT7|0x0C},
    {BK0_03_IPCTRL2, BK0_03_SYNC_Sample_Edge},
    {BK0_04_ISCTRL, 0x10},
    {BK0_10_COCTRL1, 0x20}, // COCTRL1: Analog Video Input Select

    {_END_OF_TBL_, 0x00},
};

RegUnitType code tProgMsSvPort[] =
{
    {BK0_00_REGBK, REG_BANK_SCALER},
    {BK0_02_ISELECT, _BIT7|0x0C},
    {BK0_03_IPCTRL2, BK0_03_SYNC_Sample_Edge},
    {BK0_04_ISCTRL, 0x11},
    {BK0_10_COCTRL1, 0x20}, // COCTRL1: Analog Video Input Select
    {_END_OF_TBL_, 0x00},
};

RegUnitType code tInitializeScaler[] =
{
    /////////////////////////////////////////////////
    // Initialize scaler table
    /////////////////////////////////////////////////
    {BK0_00_REGBK, REG_BANK_SCALER},

    {BK0_87_DEBUG, _BIT3}, // 20051003 John: PLL test register protect

    {BK0_01_DBFC, 0x00}, // Disable double buffer load at vertical blanking
    {BK0_02_ISELECT, 0x80},

#if (PANEL_ANALOG_TCON)
    {BK0_0D_LYL, 0x07}, // Lock Y line: 20051227.Daniel for weak signal cause panel crash
    {BK0_36_VDSUSG, 0x10},
#else
    {BK0_0D_LYL, 0x03}, // Lock Y line: 20051227.Daniel for weak signal cause panel crash
    {BK0_36_VDSUSG, 0x00},
#endif

    {BK0_0E_INTLX, 0x84}, // Using external field, enable long count
    {BK0_11_COCTRL2, 0x10},//08}, // enable coast window start for SOG/SOY(YPBPR)
    {BK0_12_COCTRL3, 0x10},//08}, // enable coast window end for SOG/SOY(YPBPR)


    {BK0_16_INTCTROL, 0x01},  // 060525 seven for SI2C

    // interrupt control
    {BK0_17_INTPULSE, 0x0f},  // interrupt pulse width by reference clock
    {BK0_18_INTSTA, 0x00},  // interrupt status byte A

    // clock generator
    {BK0_21_PLLCTRL2, 0x00}, // PLLCTRL2

    // master pll
#if (MST_CLOCK_KHZ==14318)
  	{BK0_22_MPL_M, 0x6F}, // set master pll as 215 MHz & drive current
#elif  (MST_CLOCK_KHZ==12000)
  	{BK0_22_MPL_M, 0x72}, // set master pll as 215 MHz & drive current
#endif

    // spectrum control
    {BK0_23_OPL_CTL0, 0x40}, //bit[4:0]=5'h0,LPLL_M =1
    {BK0_28_OPL_STEP0, 0x19},
    {BK0_29_OPL_STEP1, 0x01},
    {BK0_2A_OPL_SPAN0, 0xec},
    {BK0_2B_OPL_SPAN1, 0x00}, // OPL_SET sotres frame-based value

    // output dclk setting
    {BK0_24_OPL_CTL1, 0x03 }, //bit[4:3]:LPLL_P; bit[2:0]:LPLL_ICTL =3'b011

    {BK0_2C_MPL_TST, 0xC0}, // 20050520 Hans for MariaC
    {BK0_2D_OPL_TSTA0, 0x00}, // 20051003 John

    {BK0_2E_OPL_TSTA1, _BIT2|0x01}, // bit[1:0]:LPLL_K =2'b01 ,bit[2]:LPLL_TYPE,"0":LVDS,"1":TTL

    {BK0_40_VFDEST_L, LOBYTE(PANEL_DE_VSTART)},      // vertical DE start
    {BK0_41_VFDEST_H, HIBYTE(PANEL_DE_VSTART)},      // vertical DE start
    {BK0_42_HFDEST_L, LOBYTE(PanelHStart)},         // horizontal DE start
    {BK0_43_HFDEST_H, HIBYTE(PanelHStart)},         // horizontal DE start

    {BK0_44_VFDEEND_L,LOBYTE(PanelHeight- 1)},	// vertical DE end
    {BK0_45_VFDEEND_H, HIBYTE(PanelHeight - 1)}, // vertical DE end
    {BK0_46_HFDEEND_L, LOBYTE(PanelHStart+ PanelWidth- 1)},   // horizontal DE end
    {BK0_47_HFDEEND_H, HIBYTE(PanelHStart+ PanelWidth- 1)},   // horizontal DE end

    // scaling image window size
    {BK0_48_SIHST_L, LOBYTE(PanelHStart)}, // Image H start
    {BK0_49_SIHST_H, HIBYTE(PanelHStart)}, // Image H start
    {BK0_4C_SIHEND_L, LOBYTE(PanelHStart + PanelWidth - 1)}, // Image H end
    {BK0_4D_SIHEND_H, HIBYTE(PanelHStart + PanelWidth - 1)}, // Image H end

    {BK0_4A_SIVEND_L, LOBYTE(PanelHeight- 1)}, // Image V end
    {BK0_4B_SIVEND_H, HIBYTE(PanelHeight - 1)}, // Image V end
    // output Sync timing
    {BK0_4E_VDTOT_L, LOBYTE(PanelVTotal - 1)},  // output vtotal
    {BK0_4F_VDTOT_H, HIBYTE(PanelVTotal - 1)},

#if (PANEL_DIGITAL_TCON|PANEL_ANALOG_TCON)
    {BK0_50_VSST_L, LOBYTE((PanelVTotal- PanelVStart)|0x800)},  // vsync start position
    {BK0_51_VSST_H, HIBYTE((PanelVTotal- PanelVStart)|0x800)},
#else
    {BK0_50_VSST_L, LOBYTE(PanelVTotal - PanelVStart)},  // vsync start position
    {BK0_51_VSST_H, HIBYTE(PanelVTotal - PanelVStart)},
#endif

    {BK0_52_VSEND_L, LOBYTE(PanelVTotal - PanelVSyncBackPorch)},  // vsync end position
    {BK0_53_VSEND_H, HIBYTE(PanelVTotal - PanelVSyncBackPorch)},

    {BK0_54_HDTOT_L, LOBYTE(PanelHTotal- 1)}, // output htotal
    {BK0_55_HDTOT_H, HIBYTE(PanelHTotal - 1)},
    {BK0_56_HSEND, PanelHSyncWidth- 1},    // hsync end

    {BK0_57_OSCTRL1, CTRL_B|AHRT_B|SCAL_1_B|LCM_B|HSRM_B}, // Output sync control for Panel when init chip

    // dither control
#if PanelDither==6
    #if (PANEL_TYPE==PanelAU102_DT)
    {BK0_60_DITHCTRL, 0x0F},
    #elif (PANEL_TYPE==PanelINNPLUX08_DT)
    {BK0_60_DITHCTRL, 0x03},
    #else
    {BK0_60_DITHCTRL, 0x05},
    #endif
#else
    {BK0_60_DITHCTRL, 0x00},
    //{BK0_60_DITHCTRL, 0x0d}, //20050623 David tune for Gray levels is not smooth
#endif

    {BK0_61_DITHCOEF, 0x2d}, // Dither coefficient

    {BK0_86_FNTN_TEST, ((PanelSwapRB&RB_SWAP_B)|(PanelSwap6BitML&LM_SWAP6_B)|
    					(PanelSwap8BitML&LM_SWAP8_B))},

    // output sync control
    {BK0_B1_SYNC_CONTROL, (PanelDClkDelay<<4) | (CLK_INV_B&PanelInvDClk) | (DE_INV_B&PanelInvDE) |
  	                    (VS_INV_B&PanelInvVSync) | (HS_INV_B&PanelInvHSync)},

    {BK0_89_SL_TUNE_1, 0x7F},

    {BK0_8A_SL_TUNE_2, 0x01}, // Auto tune clock factor limit
    {BK0_8B_SL_TUNE_3, 0x04}, // Auto tune clock factor limit

    /////////////////////////////////////////////////
    // Initialize Common table
    /////////////////////////////////////////////////

    // initialize auto adjust
    {BK0_CB_ATOCTRL, 0x01},  // enable auto position
    {BK0_DB_ATPCTRL, 0x19},  // enable auto phase, mask 6 bits
    {BK0_C8_ATGCTRL, 0x00},  // disable auto Gain
    {BK0_DA_ATPTTH, 0x1c},  // auto phase text threshold for ATPV4

    // VSync status
    //{BK0_9B, 0x30},  // locking H total margin
    //{BK0_9E, 0x20},  // locking SSC margin

    // sync change tolerance
    {BK0_E8_HSTOL, 0x10},
    {BK0_E9_VSTOL, 0x08},

    {BK0_F7_TEST_BUS_SELECT, 0xC8},
    {BK0_F8_TEST_MODE, 0x00},

    {_END_OF_TBL_, 0x00}
};

RegUnitType code tInitializeADC[] =
{
    /////////////////////////////////////////////////
    // Initialize ADC/DVI table
    /////////////////////////////////////////////////
    {BK0_00_REGBK, REG_BANK1_ADC_ACE_MCU},

    // ADC setting
    {BK1_0E_FCOEF, 0x09}, // PLL FCOEF: For AV
    {BK1_16_DITHCTRL, 0x70}, // DITHCTRL 20050518 Apple for MariaC

    {BK1_1F, 0x55}, // 20051004 Lizst: ADC current control
    {BK1_22_TESTD2, 0x40}, // 20051004 Lizst: ADC current control

    {BK1_23_FPLL_STATUS, 0x24}, // ???: For CVBS

    {BK1_33, 0x18}, // SOG filter bandwitdh: 4.0MHz
    {BK1_34, 0x10}, // 20051007
    {BK1_35, 0x08}, // SOG trigger level for SOG/SOY(YPBPR)

    {BK1_3D, 0x14}, // ???: For CVBS
    {BK1_3E, 0x82}, // ???: For CVBS
    {BK1_3F, 0xA4}, // TST_MISC[29:24]: For CVBS
    {BK1_41, 0x88}, // ???: For CVBS
    {BK1_42, 0x80}, // ???: For CVBS

////////////////////////////////////////////////////

    {BK1_90_SARADC_CTRL, 0x20}, // SARADC_CTRL
    //{BK1_91, 0x20}, // SARADC_SAMPRD
    {BK1_92_SARADC_AISEL, 0x07}, // SARADC_AISEL

    {BK1_9C, 0x05}, // 20061027 tony

    {BK1_A0_RG_DRV,0x55},
    {BK1_A1_BS_DRV,0x55},
    {BK1_A2_CTR_DRV,0x55},

    {BK1_B6_LCK_THR_FPLL, 0x40},

    {BK1_BF_LPLL_STLMT_H, 0x01},
    {BK1_B9_COEF_FPLL, 0x7F}, // By RD:John   COEFF_FPLL
    //{BK1_C2, 0x17=default}, // Limit adjust line/pixel number
    {BK1_C3_IVS_DIFF_THR, 0x1A}, // Iuput v sync different threshold
    {BK1_C4_IVS_STALBE_THR, 0x07}, // Input v sync stable threshold

    {BK1_C5_CH_CH_MODE, 0x03},

    // PWM control
    {BK1_F3_PWMCLK, 0x69},//0x6B},//0x23},

    {BK1_F4_PWM1C, 0x00},  //0x80},  // PWM1 coarse adjustment
    {BK1_F5_PWM2C, 0x80},  // PWM2 coarse adjustment

    {BK1_F6_PWM1EPL, 0x00},
    {BK1_F7_PWM1EPH, 0xFF},

    {BK1_FC_PWM6L, 0x01}, // PWM6 freq for count input clock
    {BK1_FD_PWM6H, 0x01}, // PWM6 freq for count input clock

    {BK0_00_REGBK, REG_BANK4_LVDS_CCFL},

    {BK4_22_LVDS_T0, 0x00},//0xFF},

    {BK0_00_REGBK, REG_BANK_SCALER},

    {_END_OF_TBL_, 0x00}
};

RegUnitType code tInitializeTCON[] =
{
  {BK1_CD_GPO_OEV2_WIDTH, SET_OEV2_WIDTH},
  {BK1_CE_GPO_OEV3_WIDTH, SET_OEV3_WIDTH},
  {BK1_CF_GPO_OEV_DELTA, SET_OEV_DELTA},

  {BK1_D0_PTC_MODE1, (SET_PTC_MODE1&0x7F)},

  {BK1_D2_PTC_MODE3, SET_PTC_MODE3},