ms_reg.h

主要用于液晶电视解码,内置51单片机,全部代码用C编写,编译环境为KEILC

#define	BK3_80_CC00			0x80
#define	BK3_81_CC01			0x81
#define	BK3_82_CC02			0x82
#define	BK3_83_CC03			0x83
#define	BK3_84_CC04			0x84
#define	BK3_85_CC05			0x85
#define	BK3_86_CC06			0x86
#define	BK3_87_CC07			0x87
#define	BK3_88_CC08			0x88
#define	BK3_89_CC09			0x89
#define	BK3_8A_CC0A			0x8A
#define	BK3_8B_CC0B			0x8B
#define	BK3_8C_CC0C			0x8C
#define	BK3_8D_CC0D			0x8D
#define	BK3_8E_CC0E			0x8E
#define	BK3_8F_CC0F			0x8F
#define	BK3_90_CC10			0x90
#define	BK3_91_CC11			0x91
#define	BK3_92_CC12			0x92
#define	BK3_93_CC13			0x93
#define	BK3_94_CC14			0x94
#define	BK3_95_CC15			0x95
#define	BK3_96_CC16			0x96
#define	BK3_97_CC17			0x97
#define	BK3_98_CC18			0x98
#define	BK3_99_CC19			0x99
#define	BK3_9A_CC1A			0x9A
#define	BK3_9B_CC1B			0x9B
#define	BK3_9C_CC1C			0x9C
#define	BK3_9D_CC1D			0x9D
#define	BK3_9E_CC1E			0x9E
#define	BK3_9F_CC1F			0x9F

#define	BK3_A1_SCM_IDSET1		0xA1
#define	BK3_A2					0xA2

#define	BK3_A4_LINE_START_A	0xA4
#define	BK3_A5_LINE_START_B	0xA5

#define	BK3_A7_LINE_LENGTH	0xA7
#define	BK3_A8_ACT_MULTIPLE	0xA8
#define	BK3_A9					0xA9
#define	BK3_AA					0xAA
#define	BK3_AB					0xAB
#define	BK3_AC					0xAC
#define	BK3_AD					0xAD
#define	BK3_AE					0xAE
#define	BK3_AF					0xAF

#define	BK3_B0					0xB0
#define	BK3_B1					0xB1
#define	BK3_B2					0xB2
#define	BK3_B3					0xB3
#define	BK3_B4					0xB4
#define	BK3_B5					0xB5

#define	BK3_B9					0xB9

#define	BK3_C5					0xC5

#define	BK3_F2_WR_LK1			0xF2
#define	BK3_F3_PWMCLK			0xF3
#define	BK3_F4_PWM3C			0xF4
#define	BK3_F5_PWM4C			0xF5
#define	BK3_F6_PWM3EPL		0xF6
#define	BK3_F7_PWM3EPH		0xF7
#define	BK3_F8_PWM4EPL		0xF8
#define	BK3_F9_PWM4EPH		0xF9
//=====================================================================
// Bank = 04 (LVDS & CCFL Register)
#define BK4_10_GPOA_CTRL	0x10
#define BK4_11_GAVST_L		0x11
#define BK4_12_GAVST_H		0x12
#define BK4_13_GAVEND_L	0x13
#define BK4_14_GAVEND_H	0x14
#define BK4_15_GAHST_L		0x15
#define BK4_16_GAHST_H		0x16
#define BK4_17_GAHEND_L	0x17
#define BK4_18_GAHEND_H	0x18
#define BK4_19_LVDS_CTRL	0x19
#define BK4_1A_LVDS_TEST	0x1A
#define BK4_1B_MOD_TDR0	0x1B
#define BK4_1C_MOD_TDR1	0x1C
#define BK4_1D_MOD_TDR2	0x1D
#define BK4_1E_MOD_CTRL	0x1E

#define BK4_20_MOD_SEL0	0x20
#define BK4_21_MOD_SEL1	0x21
#define BK4_22_LVDS_T0		0x22
#define BK4_23_LVDS_T1		0x23
#define BK4_24_LVDS_TRI0	0x24
#define BK4_25_LVDS_TRI1	0x25

#define BK4_6B				0x6B
#define BK4_6C				0x6C
#define BK4_6D				0x6D
#define BK4_6E				0x6E
#define BK4_6F				0x6F

#define BK4_70				0x70
#define BK4_71				0x71
#define BK4_72				0x72
#define BK4_73				0x73
#define BK4_74				0x74
#define BK4_75				0x75
#define BK4_76				0x76
#define BK4_77				0x77
#define BK4_78				0x78
#define BK4_79				0x79
#define BK4_7A				0x7A
#define BK4_7B				0x7B
#define BK4_7C				0x7C
#define BK4_7D				0x7D
#define BK4_7E				0x7E
#define BK4_7F				0x7F

#define BK4_80				0x80
#define BK4_81				0x81
#define BK4_82				0x82
#define BK4_83				0x83
#define BK4_84		 		0x84
#define BK4_85				0x85
#define BK4_86				0x86
#define BK4_87				0x87
#define BK4_88				0x88
#define BK4_89				0x89
#define BK4_8A				0x8A
#define BK4_8B				0x8B
#define BK4_8C				0x8C
#define BK4_8D				0x8D
#define BK4_8E				0x8E
#define BK4_8F				0x8F

#define BK4_90				0x90
#define BK4_91				0x91
#define BK4_92				0x92
#define BK4_93				0x93
#define BK4_94				0x94
#define BK4_95				0x95
#define BK4_96				0x96
#define BK4_97				0x97
#define BK4_98				0x98
#define BK4_99				0x99
#define BK4_9A				0x9A
#define BK4_9B				0x9B
#define BK4_9C				0x9C
#define BK4_9D				0x9D
#define BK4_9E				0x9E
#define BK4_9F				0x9F

#define BK4_A0				0xA0
#define BK4_A1				0xA1
#define BK4_A2				0xA2
#define BK4_A3				0xA3
#define BK4_A4				0xA4
#define BK4_A5				0xA5
#define BK4_A6				0xA6
#define BK4_A7				0xA7
#define BK4_A8				0xA8
#define BK4_A9				0xA9
#define BK4_AA				0xAA
#define BK4_AB				0xAB
#define BK4_AC				0xAC
#define BK4_AD				0xAD
#define BK4_AE				0xAE
#define BK4_AF				0xAF

#define BK4_B0				0xB0
#define BK4_B1				0xB1
#define BK4_B2				0xB2

#define DSP_10				0x10
#define DSP_11				0x11
#define DSP_20				0x20
#define DSP_21				0x21
#define DSP_14				0x14
#define DSP_18				0x18
#define DSP_2A				0x2A
#define DSP_3C				0x3C
#define DSP_84				0x84
#define DSP_00				0x00
#define DSP_0F				0x0F
#define DSP_3A				0x3A
#define DSP_3B				0x3B

//=====================================================================

//---------------------------OSD register-------------------
// osd double buffer control
#define	OSD_01_OSDDBC			0x01
// osd start position
#define	OSD_02_OHSTA_L		0x02
#define	OSD_03_OHSTA_H		0x03
#define	OSD_04_OVSTA_L 		0x04
#define	OSD_05_OVSTA_H 		0x05
// osd size controol
#define	OSD_06_OSDW			0x06
#define	OSD_07_OSDH			0x07
// osd space control
#define	OSD_08_OHSPA			0x08
#define	OSD_09_OVSPA			0x09
#define	OSD_0A_OSPW			0x0A
#define	OSD_0B_OSPH			0x0B
// internal osd control
#define	OSD_0C_IOSDC1			0x0C
	#define	MWIN_B			_BIT0
#define	OSD_0D_IOSDC2			0x0D
#define	OSD_0E_IOSDC3			0x0E
#define	OSD_10_IOSDC4			0x10
//osd windodw shadow control
#define	OSD_0F_OSHC			0x0F
//osd code buffer offset/ base address
#define	OSD_12_OCBUFO			0x12
#define	OSD_13_OSDBA_L 		0x13
#define	OSD_14_OSDBA_H 		0x14
// osd gradually color control
#define	OSD_15_GCCTRL			0x15
#define	OSD_16_GRADCLR 		0x16
// osd horizontal gradullay color
#define	OSD_17_HGRADCR 		0x17
#define	OSD_18_HGRADCG 		0x18
#define	OSD_19_HGRADCB 		0x19
#define	OSD_1A_HGRADSR 		0x1A
#define	OSD_1B_HGRADSG 		0x1B
#define	OSD_1C_HGRADSB 		0x1C
// osd vertical gradullay color
#define	OSD_1D_VGRADCR 		0x1D
#define	OSD_1E_VGRADCG 		0x1E
#define	OSD_1F_VGRADCB 		0x1F
#define	OSD_20_VGRADSR 		0x20
#define	OSD_21_VGRADSG 		0x21
#define	OSD_22_VGRADSB 		0x22
//
#define	OSD_26_TIMECTRL		0x26
#define	OSD_27_OSDRTP			0x27
// osd color palette
#define	OSD_28_CLR0R			0x28
#define	OSD_29_CLR0G			0x29
#define	OSD_2A_CLR0B			0x2A
#define	OSD_2B_CLR1R			0x2B
#define	OSD_2C_CLR1G			0x2C
#define	OSD_2D_CLR1B			0x2D
#define	OSD_2E_CLR2R			0x2E
#define	OSD_2F_CLR2G			0x2F
#define	OSD_30_CLR2B			0x30
#define	OSD_31_CLR3R			0x31
#define	OSD_32_CLR3G			0x32
#define	OSD_33_CLR3B			0x33
#define	OSD_34_CLR4R			0x34
#define	OSD_35_CLR4G			0x35
#define	OSD_36_CLR4B			0x36
#define	OSD_37_CLR5R			0x37
#define	OSD_38_CLR5G			0x38
#define	OSD_39_CLR5B			0x39
#define	OSD_3A_CLR6R			0x3A
#define	OSD_3B_CLR6G			0x3B
#define	OSD_3C_CLR6B			0x3C
#define	OSD_3D_CLR7R			0x3D
#define	OSD_3E_CLR7G			0x3E
#define	OSD_3F_CLR7B			0x3F
//
#define	OSD_40_SCRLSPD		0x40
#define	OSD_41_SCRLLINE		0x41
#define   OSD_42_UNDERLINE		0x42
#define	OSD_43_TRUNCATE		0x43
#define	OSD_44_ITALIC			0x44
#define	OSD_45_MISC_CTL		0x45
#define 	OSD_46_OSD4CFFA		0x46


//---------------------------MCU register-------------------
// ISP control
#define sfRegs          ((unsigned char volatile xdata *)0xC000)
#define	ISP_DEVA		0xC000			// ISP device address
#define	ISP_PWD1		0xC001			// ISP password 1
#define	ISP_PWD2		0xC002			// ISP password 2
#define	ISP_PWD3		0xC003			// ISP password 3
#define	ISP_PWD4		0xC004			// ISP password 4
#define	ISP_PWD5		0xC005			// ISP password 5
#define	SOFT_ISP		0xC006			// Write 93h to enable ISP mode

// Watch dog control
#define	WDT_KEY_L		0xC008			// Default:0xAA
#define	WDT_KEY_H		0xC009			// Default:0x55

// Serial DEBUG control
#define	SR_DB_CTRL		0xC00A			//[7:1]:Serial DEBUG mode device address;[0]:Disable

// DDC2BI control
#define	DDC2BI_INT_EN		0xC010			// DDC 2Bi interrupt enable

#define	DDC2BI_FLAG		0xC011			// DDC 2Bi interrupt flag and clear
#define	DDC2BI_W_BUF		0xC012			// DDC 2Bi write, MCU read buffer
#define	DDC2BI_R_BUF		0xC013			// DDC 2Bi read, MCU write buffer
#define	DDC2BI_CTRL		0xC018			//
#define	DDC2BI_ID		0xC019			//


// I/O port control
#define	P0_CTRL			0xC030			// MCU port 0 output enable control
#define	P0_OE			0xC031			// MCU port 0 output enable
#define	P0_IN			0xC032			// MCU port 0 output enable from output data
#define	P1_CTRL 		0xC033			// MCU port 1 output enable control
#define	P1_OE			0xC034			// MCU port 1 output enable
#define	P1_IN			0xC035			// MCU port 1 output enable from output data
#define	P2_CTRL 		0xC036			// MCU port 2 output enable control
#define	P2_OE			0xC037			// MCU port 2 output enable
#define	P2_IN			0xC038			// MCU port 2 output enable from output data
#define	P3_CTRL 		0xC039			// MCU port 3 output enable control
#define	P3_OE			0xC03A			// MCU port 3 output enable
#define	P3_IN			0xC03B			// MCU port 3 output enable from output data
#define	P4_CTRL 		0xC03C			// MCU port 4 output enable control
#define	P4_OE			0xC03D			// MCU port 4 output enable
#define	P4_IN			0xC03E			// MCU port 4 output enable from output data


// Parallel flash ISP control
#define	ISP_PA_0		0xC050			// Parallel flash ISP address[7:0]
#define	ISP_PA_1		0xC051			// Parallel flash ISP address[15:8]
#define	ISP_PA_2		0xC052			// [1:0]:Parallel flash ISP address[17:16]
#define	ISP_PD_W		0xC053			// Parallel flash ISP write data
#define	ISP_PCTR		0xC054			// Parallel flash ISP control
#define	ISP_PD_R		0xC055			// Parallel flash ISP mode read data

//=====================================================================