ms_reg.h

主要用于液晶电视解码,内置51单片机,全部代码用C编写,编译环境为KEILC

//
// MST7XXX registers define
// 2005/1/6
//
#define	BK0_00_REGBK					0x00			// Register Bank Select
	#define	AINC_B						_BIT3		// Serial bus address auto increase (Enable|Disable)
	#define	REG_BANK_MASK				0x07		// [1:0]:Register Bank Select
	#define	REG_BANK_SCALER				0x0		// Scaler Bank
	#define	REG_BANK1_ADC_ACE_MCU		0x1		// ADC/ACE/MCU Bank
	#define	REG_BANK2_VD				0x2		// Video Decoder Front End Bank
	#define	REG_BANK3_COMB				0x3		// Video Decoder 2D Comb Filter Bank
	#define	REG_BANK4_LVDS_CCFL			0x4
//=====================================================================
// Bank = 00 (Scaler Register)
// Double buffer control
#define	BK0_01_DBFC			0x01			// enable dobule buffer while vertical blanking
	#define	DBC_B			_BIT0		// Enable or Disable
	//DBL[1:0]
	#define	DBL_0			0		// Keep old register value
	#define	DBL_1			2		// Load new data (auto reset to 00 when load finish)
	#define	DBL_2			4		// Automatically load data at VSYNC blanking
	#define	DBL_3			6		// Reserved

#define	BK0_02_ISELECT			0x02
	#define	EXTVD_B		_BIT0		// External Video Decoder select
	#define	BYPASSMD_B		_BIT1		// By pass mode for interlace-input-interlace-output
	#define	IHSU_B			_BIT2		// Input Sync Usage
	#define	ICS_B			_BIT3		// CSC function enable
	#define	COMP_B			_BIT4		// CSYNC/SOG select (only useful when STYPE = 00)
	#define	NIS_B			_BIT7		// Input Source Enable
	#define	STYPE_Mask		0x60		// [6:5]:Input Sync Tpye


#define	BK0_03_IPCTRL2			0x03
	#define	HWRP_B			_BIT0		// input horizontal wrap
	#define	VWRP_B			_BIT1		// input vertical wrap
	#define	ESLS_B			_BIT2		// early sample line select
	#define	VSE_B			_BIT3		// input vsync reference edge
	#define	HSE_B			_BIT4		// input hsync reference edge
	#define	IVSD_B			_BIT5		// vsync delay select
	#define	VDS_AVG_B		_BIT6		// input data double sample using average
	#define	VDS_EN_B		_BIT7		// input data double sample Enable

#define	BK0_04_ISCTRL			0x04
	#define	MVD_SEL_Mask		0x03		// [1:0]:MVD Mode Select
	#define	MVD_SELCVBS		0x0		// CVBS
	#define	MVD_SELSVideo		0x1		// S-Video
	#define	MVD_SELYCbCr		0x2		// YCbCr
	#define	MVD_SELRGB		0x3		// RGB
	#define	ISSM_B			_BIT2		// Input sync sample mode (Glitch-removal)
	#define	HSFL_B			_BIT3		// Input HSYNC Filter on
	#define	DEGR_Mask		0x70		// [6:4]:DE or HSYNC post Glitch removal Range
	#define	DDE_B			_BIT7		// Direct DE mode for CCIR input

// Input image sample range
#define	BK0_05_SPRVST_L		0x05			// Image vertical sample star point, count by input HSYNC
#define	BK0_06_SPRVST_H		0x06			// [10:0]
#define	BK0_07_SPRHST_L		0x07			// Image horizontal sample star point, count by input dot clock
#define	BK0_08_SPRHST_H		0x08			// [10:0]
#define	BK0_09_SPRVDC_L		0x09			// Image vertical resolution (vertical display enable area count by line)
#define	BK0_0A_SPRVDC_H		0x0A			// [10:0]
#define	BK0_0B_SPRHDC_L		0x0B			// Image horizontal resolution (vertical display enable area count by pixel)
#define	BK0_0C_SPRHDC_H		0x0C			// [10:0]
#define	BK0_0D_LYL			0x0D			// Lock Y line [3:0]

#define	BK0_0E_INTLX			0x0E
	#define	IntLac_LockAVG_B	_BIT3		//
	#define	VDOE_B			_BIT4		// Video reference Edge (for non-standard signal)

#define	BK0_0F_ASCTRL			0x0F
	#define	OVER_B			_BIT0		// Over run status(RO)
	#define	UNDER_B		_BIT1		// Under run status(RO)
	#define	INTLAC_SETSTD_B	_BIT2		// NTSC/PAL Setting in Manual Mode Under run status
	#define	INTLAC_MANSTD_B	_BIT3		// NTSC/PAL Manual Mode
	#define	DLINE_Mask		0x30		// [5:4]:Delay Line
	#define	IVB_B			_BIT7		// Input VSYNC Blanking Status(RO)

#define	BK0_10_COCTRL1			0x10
	#define	CTA_B			_BIT0		// Coast to ADC
	#define	COVS_B			_BIT1		// Coast VSYNC Select
	#define	EXVS_B			_BIT2		// External VSYNC polarity (only used when COVS is 1)
	#define	CSCM_B			_BIT3		// Composite SYNC cut mode
	#define	DLYV_B			_BIT4		// Analog Delay Line for component analog Video input
	#define	ASIS_B			_BIT5		// Analog Video Input Select(0:PC 1:Component analog video)

#define	BK0_11_COCTRL2			0x11			// Front tuning (Coast start from 1~256 HSYNC leading edge) COST[7:0]
#define	BK0_12_COCTRL3			0x12			// End tuning (Coast end at 1~256 HSYNC leading edge) COEND[7:0]

// Interrupt setting
#define	BK0_16_INTCTROL		0x16
	#define	INTT_B			_BIT0		// Interrupt Trigger
	#define	TRGC_B			_BIT1		// Trigger Condition
	#define	OVSI_B			_BIT2		// Output VSYNC interrupt generated Condition
	#define	IVSI_B			_BIT3		// Input VSYNC interrupt generated Condition
	#define	CHG_HMD_B		_BIT7		// H Change Mode for INT

#define	BK0_17_INTPULSE		0x17			// Interrupt Pulse Width by reference clock (BK0_17_INTPULSE[7:0])
#define	BK0_18_INTSTA			0x18			// Interrupt Status byte A
#define	BK0_19_INTENA			0x19			// Interrupt Enable control byte A
#define	BK0_1A_INTSTB			0x1A			// Interrupt Status byte B
#define	BK0_1B_INTENB			0x1B			// Interrupt Enable control byte B
#define	BK0_1C_INTSTC			0x1C			// Interrupt Status byte C
#define	BK0_1D_INTENC			0x1D			// Interrupt Enable control byte C
#define	BK0_1E_INTSTD			0x1E			// Interrupt Status byte D
#define	BK0_1F_INTEND			0x1F			// Interrupt Enable control byte D

// PLL control
#define	BK0_21_PLLCTRL2		0x21
	#define	MPL_PD_B 		_BIT0		// Master PLL Power down
	#define	MPL_RST_B		_BIT1		// Master PLL reset
	#define	MPL_POR_B		_BIT2		// Master PLL power on reset
	#define	MPL_K_B		_BIT3		// Master PLL Post output frequency divided by 2
	#define	OLP_PD_B 		_BIT4		// output PLL power down
	#define	OLP_RST_B		_BIT5		// output PLL reset
	#define	OLP_POR_B		_BIT6		// output PLL power on reset

#define	BK0_22_MPL_M			0x22
	// [7:5] MP_ICTRL[2:0]		Master PLL Current Contrl
	// [4:0] MPL_M[4:0]		Master PLL divider
#define	BK0_23_OPL_CTL0		0x23

	// [3:0] OPL_N[3:0]		Output PLL feedback divider
	#define	SDMD_B			_BIT5		// Output PLL spread spectrum Mode
	#define	SSC_EN_B		_BIT6		// Output PLL spread spectrum


#define	BK0_24_OPL_CTL1		0x24
	// [7:6] SCTRL[1:0]		SSC Control
	// [4:3] OPL_P[1:0]		Output PLL post divider
	// [2:0] OPL_ICTRL		Output PLL Current Control

// Output PLL Set
#define	BK0_25_OPL_SET0		0x25			// Output PLL set:OPL_SET[7:0]
#define	BK0_26_OPL_SET1		0x26			// OPL_SET[15:8]
#define	BK0_27_OPL_SET2		0x27			// OPL_SET[23:16]
#define	BK0_28_OPL_STEP0		0x28			// Output PLL spread spectrun step:OPL_STEP[7:0]
#define	BK0_29_OPL_STEP1		0x29
	// [2:0] OPL_STEP[10:8]
	#define	OPL_EXTSEL_B		_BIT5		// Output PLL external clock select
	#define	OPL_EXTEN_B		_BIT6		// Output PLL external clock mode enable
	#define	OPL_BYPS_B		_BIT7		// Bypass output PLL

#define	BK0_2A_OPL_SPAN0		0x2A			// Output PLL spread spectrum span: OPL_SPAN[7:0]
#define	BK0_2B_OPL_SPAN1		0x2B
	// [6:0] OPL_SPAN[14:8]
	#define	READ_FRAME_B		_BIT7		// 0/1: OPL_SET stores line-based/frame-based value

#define	BK0_2C_MPL_TST		0x2C			// MPL_TEST[7:0]
#define	BK0_2D_OPL_TSTA0		0x2D			// OPL_TESTA[7:0]
#define	BK0_2E_OPL_TSTA1		0x2E			// OPL_TESTA[15:8]
#define	BK0_2F_OPL_TSTD		0x2F			// OPL_TEST[7:0]

// Horizontal scaling ratio
#define	BK0_30_SRH_L			0x30			// SRH[7:0]
#define	BK0_31_SRH_M			0x31			// SRH[15:8]
#define	BK0_32_SRH_H			0x32
	// [3:0] SRH[19:16]
	#define	SENH_B			_BIT7		// Enable Horizontal scaling
	#define	CBILINEAR_B		_BIT6		// Complmental Bi-Linear Enable
	#define	FORCEBICOLOR_B	_BIT5		// 0:Chrominance using same setting as Luminance defined by _BIT6
							// 1:Chrominance always using Bi-Linear algorithm
// Vertical scaling ratio
#define	BK0_33_SRV_L			0x33			// SRV[7:0]
#define	BK0_34_SRV_M			0x34			// SRV[15:8]
#define	BK0_35_SRV_H			0x35
	// [5:0] SRV[21:16]
	#define	SENV_B			_BIT7		// Enable Vertical scaling

#define	BK0_36_VDSUSG			0x36
	#define	LBICLK_DIV2_B		_BIT1		// Line-buffer clock frequency is divider by 2
	#define	VSFIELDINV_B		_BIT2		// Offset inverting for even/odd scaling
	#define	VSFIELDEN_B		_BIT3		// Enable offset for even/odd scaling
	#define	ODCLK_DIV3_B		_BIT4		// Output clock is 1/3 frequency of opll output
	#define	LB_NOGATEMD_B		_BIT5		// Line-buffer always live
	#define	LBI_ODCLKMD_B		_BIT6		// Line-buffer using output clock
	#define	LBI_IDCLKMD_B		_BIT7		// Line-buffer using input clock

// Non-Linear scaling
#define	BK0_38_NLDTI			0x38
	//[6:0] NLDIO[6:0]		Non-Linear scaling section Initial Offset
	#define	NL_EN_B		_BIT7		// Non-Linear scaling enable

#define	BK0_39_NLDT0			0x39			// Non-Linear scaling Delta for Section 0, bit 7 is sign bit
#define	BK0_3A_NLDT1			0x3A			// Non-Linear scaling Delta for Section 1, bit 7 is sign bit
#define	BK0_3B_NLDC0			0x3B			// Non-Linear scaling Section 0 Dot Count/2
#define	BK0_3C_NLDC1			0x3C			// Non-Linear scaling Section 1 Dot Count/2
#define	BK0_3D_NLDC2			0x3D			// Non-Linear scaling Section 2 Dot Count/2


// Display Timing
#define	BK0_40_VFDEST_L		0x40			// Output frame DE Vertical Start [7:0]
#define	BK0_41_VFDEST_H		0x41			// VFDEST[10:8] at [2:0]
#define	BK0_42_HFDEST_L		0x42			// Output frame DE Horizontal Start [7:0]
#define	BK0_43_HFDEST_H		0x43			// HFDEST[10:8] at [2:0]
#define	BK0_44_VFDEEND_L		0x44			// Output frame DE Vertical END [7:0]
#define	BK0_45_VFDEEND_H		0x45			// VFDEEND[10:8] at [2:0]
#define	BK0_46_HFDEEND_L		0x46			// Output frame DE Horizontal END [7:0]
#define	BK0_47_HFDEEND_H		0x47			// HFDEEND[10:8] at [2:0]


// Scaling image window size
#define	BK0_48_SIHST_L			0x48			// Scaling Image window Horizontal Start [7:0]
#define	BK0_49_SIHST_H		0x49			// SIHST[10:8] at [2:0]
#define	BK0_4A_SIVEND_L		0x4A			// Scaling Image window Vertical END [7:0]
#define	BK0_4B_SIVEND_H		0x4B			// SIVEND[10:8] at [2:0]
#define	BK0_4C_SIHEND_L		0x4C			// Scaling Image window Horizontal END [7:0]
#define	BK0_4D_SIHEND_H		0x4D			// SIHEND[10:8] at [2:0]

// Output sync timing
#define	BK0_4E_VDTOT_L		0x4E			// Output Vertical Total [7:0]
#define	BK0_4F_VDTOT_H		0x4F			// VDTOT[10:8] at [2:0]
#define	BK0_50_VSST_L			0x50			// Output VSYNC start ( only useful when AOVS=1) [7:0]
#define	BK0_51_VSST_H			0x51			// VSST[10:8] at [2:0]
	#define	VSRU_B			_BIT3		// VSYNC Register Usage
#define	BK0_52_VSEND_L		0x52			// Output VSYNC END ( only useful when AOVS=1) [7:0]
#define	BK0_53_VSEND_H		0x53			// VSEND[10:8] at [2:0]
#define	BK0_54_HDTOT_L		0x54			// Output Horizontal Total [7:0]
#define	BK0_55_HDTOT_H		0x55			// HDTOT[10:8] at [2:0]
#define	BK0_56_HSEND			0x56			// Output HSYNC pulse width

// Output sync control
#define	BK0_57_OSCTRL1		0x57
	#define	CTRL_B			_BIT0		// ATCTRL function enable
	#define	AHRT_B			_BIT1		// Auto H total and Read start Tuning enable
	#define	SCAL_1_B		_BIT2		// Scaling range add 1
	#define	HSRM_B			_BIT5		// HSYNC Remove Mode
	#define	LCM_B			_BIT6		// Frame Lock Mode
	#define	AVOS_B			_BIT7		// Auto Output VSYNC

// Brightness control
#define	BK0_58_BRIGHTNESS_EN			0x58
	#define BRI_EN_B			_BIT0		// Brightness function enable
#define	BK0_59_BRI_R			0x59			// Brightness coefficient - Red color
#define	BK0_5A_BRI_G			0x5A			// Brightness coefficient - Green color
#define	BK0_5B_BRI_B			0x5B			// Brightness coefficient - Blue color

// Frame color
#define	BK0_5C_FRAME_COLOR_1		0x5C
	#define	FC_EN_B		_BIT0		// Enable frame color
	//[7:6]: frame color G[4:3]
	//[5:1]: frame color B[7:3]
#define	BK0_5D_FRAME_COLOR_2		0x5D
	//[7:3]: frame color R[7:3]
	//[2:0]: frame color G[7:5]
#define	BK0_5E_PATTERN		0x5E
	#define	REVERSE_B		_BIT0		// BK0_5E_PATTERN white
	#define	BLACK_B		_BIT1		// BK0_5E_PATTERN black
	#define	WHITE_B		_BIT2		// BK0_5E_PATTERN reverse

// External OSD control
#define	BK0_5F_EXT_OSD_CNTRL		0x5F
	#define	B_KEY_B		_BIT0		// Key B color selected
	#define	G_KEY_B		_BIT1		// Key G color selected
	#define	R_KEY_B		_BIT2		// Key R color selected
	#define	EN_NOTEKEY_B		_BIT3		// Enable inverse color key
	#define	EN_CKEY_B		_BIT4		// Enable color key
	#define	EOSDEXT_Mask		0x60		// Data extend mode
	#define	EN_EXTOSD_B		_BIT7		// Enable external osd function

// Dither function control
#define	BK0_60_DITHCTRL		0x60
	#define	DITH_B			_BIT0		// Enable Dither function
	#define	OBN_B			_BIT1		// Output Bits Number 0/1:8/6
	#define	TROT_B			_BIT2		// Temporal coefficient Rotate
	#define	SROT_B			_BIT3		// Spatial coefficient Rotate
	#define	DITHB_Mask		0x30		// [5:4]:Dither coefficient for B channel
	#define	DITHG_Mask		0xC0		// [7:6]:Dither coefficient for G channel

#define	BK0_61_DITHCOEF		0x61
	#define	BR_Mask		0x03		// [1:0]:Bottom - Right dither coefficient
	#define	BL_Mask		0x0C		// [3:2]:Bottom - Left dither coefficient
	#define	TR_Mask		0x30		// [5:4]:Top - right dither coefficient
	#define	TL_Mask		0xC0		// [7:6]:Top - Left dither coefficient

#define	BK0_62_DITHCTL1		0x62
	#define	ABM_Mask		0x07		// [2:0]:Alpha Blending Mode
	#define	DITHERMINUS_B		_BIT3
	#define	PSEUDO_EN_B		_BIT4
	#define	AUTODITHER_B		_BIT5
	#define	NDMD_B			_BIT6		// Noise Dithering Method
	#define	PSRD_B			_BIT7		// Disable Pandom, reset every 4 frames

#define	BK0_63_OSD_CTL			0x63
	#define	OBM_Mask		0x07		// [2:0]:Osd Blend Mode
	#define	NBM_B			_BIT3		// New Blend Method
	#define	CKIND_Mask		0xF0		// [7:4]:Color Index of Color Key

// Color Matrix function
#define BK0_64_CM11_L			0x64		// Color Matrix Coefficient 11 [7:0]
#define BK0_65_CM11_H			0x65		// CM11[12:8] at [4:0]
#define BK0_66_CM12_L			0x66		// Color Matrix Coefficient 12 [7:0]
#define BK0_67_CM12_H			0x67		// CM12[12:8] at [4:0]
#define BK0_68_CM13_L			0x68		// Color Matrix Coefficient 13 [7:0]
#define BK0_69_CM13_H			0x69		// CM13[12:8] at [4:0]
#define BK0_6A_CM21_L			0x6A		// Color Matrix Coefficient 21 [7:0]
#define BK0_6B_CM21_H			0x6B		// CM21[12:8] at [4:0]
#define BK0_6C_CM22_L			0x6C		// Color Matrix Coefficient 22 [7:0]
#define BK0_6D_CM22_H			0x6D		// CM22[12:8] at [4:0]
#define BK0_6E_CM23_L			0x6E		// Color Matrix Coefficient 23 [7:0]
#define BK0_6F_CM23_H			0x6F		// CM23[12:8] at [4:0]
#define BK0_70_CM31_L			0x70		// Color Matrix Coefficient 31 [7:0]
#define BK0_71_CM31_H			0x71		// CM31[12:8] at [4:0]
#define BK0_72_CM32_L			0x72		// Color Matrix Coefficient 32 [7:0]
#define BK0_73_CM32_H			0x73		// CM32[12:8] at [4:0]
#define BK0_74_CM33_L			0x74		// Color Matrix Coefficient 33 [7:0]
#define BK0_75_CM33_H			0x75		// CM33[12:8] at [4:0]

#define	BK0_76_COL_MATRIX_CTL	0x76
	#define	BRAN_B			_BIT0		// Blue Range 0/1:0~255/128~127
	#define	GRAN_B			_BIT1		// Green Range 0/1:0~255/128~127
	#define	RRAN_B			_BIT2		// Red Range 0/1:0~255/128~127
	#define	CMC_B			_BIT4		// Color Matrix Control 1:Enable
	#define	CMRND_B		_BIT5		// Color Matrix Rounding Control 1:Enable

//
#define	BK0_77_FBL_CTL			0x77
	#define	SLN_Mask		0x07		// [2:0]: Shift Line Numbers
	#define	ODDF_B			_BIT3		// Shift Odd Field

#define	BK0_78_LCK_VCNT_L		0x78			// Lock vtotal[7:0]
#define	BK0_79_LCK_VCNT_H		0x79			// Lock_vcnt[10:8] at [2:0]
#define	BK0_7A_CAP_VCNT_L		0x7A			// cap vtotal[7:0]
#define	BK0_7B_CAP_VCNT_H		0x7B			// cap_vcnt[10:8] at [2:0]
#define	BK0_7C_CAP_HCNT_L		0x7C			// cap htotal[7:0]
#define	BK0_7D_CAP_HCNT_H		0x7D			// cap_hcnt[10:8] at [2:0]
#define	BK0_7E_EST_VCNT_L		0x7E			// est vtotal[7:0]
#define	BK0_7F_EST_VCNT_H		0x7F			// est_vcnt[10:8] at [2:0]
#define	BK0_80_EST_HCNT_L		0x80			// est htotal[7:0]
#define	BK0_81_EST_HCNT_H		0x81			// est_hcnt[10:8] at [2:0]