i2s.c

基于TI公司Cortex-M3的uart超级通信开发

    //
    // Enable the Rx FIFO service request.
    //
    HWREG(ulBase + I2S_O_RXISM) = I2S_RXISM_FFM;

    //
    // Enable the transmit and receive modules.
    //
    HWREG(ulBase + I2S_O_CFG) |= I2S_CFG_TXEN | I2S_CFG_RXEN;
}

//*****************************************************************************
//
//! Disables the I2S transmit and receive modules.
//!
//! \param ulBase is the I2S module base address.
//!
//! This function simultaneously disables the transmit and receive modules.
//! When the module is disabled, no data or clocks will be generated on the I2S
//! signals.
//!
//! \return None.
//
//*****************************************************************************
void
I2STxRxDisable(unsigned long ulBase)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == I2S0_BASE);

    //
    // Disable the transmit and receive modules.
    //
    HWREG(ulBase + I2S_O_CFG) &= ~(I2S_CFG_TXEN | I2S_CFG_RXEN);
}

//*****************************************************************************
//
//! Configures the I2S transmit and receive modules.
//!
//! \param ulBase is the I2S module base address.
//! \param ulConfig is the logical OR of the configuration options.
//!
//! This function is used to configure the options for the I2S transmit and
//! receive channels with identical parameters.  The parameter \e ulConfig is
//! the logical OR of the following options:
//!
//! - \b I2S_CONFIG_FORMAT_I2S for standard I2S format,
//! \b I2S_CONFIG_FORMAT_LEFT_JUST for left justified format, or
//! \b I2S_CONFIG_FORMAT_RIGHT_JUST for right justified format.
//! - \b I2S_CONFIG_SCLK_INVERT to invert the polarity of the serial bit clock.
//! - \b I2S_CONFIG_MODE_DUAL for dual channel stereo,
//! \b I2S_CONFIG_MODE_COMPACT_16 for 16-bit compact stereo mode,
//! \b I2S_CONFIG_MODE_COMPACT_8 for 8-bit compact stereo mode, or
//! \b I2S_CONFIG_MODE_MONO for single channel mono format.
//! - \b I2S_CONFIG_CLK_MASTER or \b I2S_CONFIG_CLK_SLAVE to select whether
//! the I2S transmitter is the clock master or slave.
//! - \b I2S_CONFIG_SAMPLE_SIZE_32, \b _24, \b _20, \b _16, or \b _8
//! to select the number of bits per sample.
//! - \b I2S_CONFIG_WIRE_SIZE_32, \b _24, \b _20, \b _16, or \b _8
//! to select the number of bits per word that are transferred on the data
//! line.
//! - \b I2S_CONFIG_EMPTY_ZERO or \b I2S_CONFIG_EMPTY_REPEAT to select whether
//! the module transmits zeroes or repeats the last sample when the FIFO is
//! empty.
//!
//! \return None.
//
//*****************************************************************************
void
I2STxRxConfigSet(unsigned long ulBase, unsigned long ulConfig)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == I2S0_BASE);
    ASSERT((ulConfig & (I2S_CONFIG_FORMAT_MASK | I2S_CONFIG_MODE_MASK |
                        I2S_CONFIG_EMPTY_MASK | I2S_CONFIG_CLK_MASK |
                        I2S_CONFIG_SAMPLE_SIZE_MASK |
                        I2S_CONFIG_WIRE_SIZE_MASK)) == ulConfig);

    //
    // Clear out any prior configuration of the FIFO config registers.
    //
    HWREG(ulBase + I2S_O_TXFIFOCFG) = 0;
    HWREG(ulBase + I2S_O_RXFIFOCFG) = 0;

    //
    // If mono mode is used, then the FMM bit needs to be set.
    //
    if((ulConfig & I2S_CONFIG_MODE_MASK) == I2S_CONFIG_MODE_MONO)
    {
        HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_FMM;
        ulConfig &= ~(I2S_CONFIG_MODE_MONO);
    }

    //
    // If a compact mode is used, then the CSS bit needs to be set.
    //
    if((ulConfig & I2S_CONFIG_MODE_MASK) == I2S_CONFIG_MODE_COMPACT_8)
    {
        HWREG(ulBase + I2S_O_TXFIFOCFG) |= I2S_TXFIFOCFG_CSS;
        HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_CSS;
    }

    //
    // Write the configuration register.  Since all the fields are specified by
    // the configuration parameter, it is not necessary to do a
    // read-modify-write.
    //
    HWREG(ulBase + I2S_O_TXCFG) = ulConfig;
    HWREG(ulBase + I2S_O_RXCFG) = ulConfig;
}

//*****************************************************************************
//
//! Selects the source of the master clock, internal or external.
//!
//! \param ulBase is the I2S module base address.
//! \param ulMClock is the logical OR of the master clock configuration
//! choices.
//!
//! This function selects whether the master clock is sourced from the device
//! internal PLL, or comes from an external pin.  The I2S serial bit clock
//! (SCLK) and left-right word clock (LRCLK) are derived from the I2S master
//! clock.  The transmit and receive modules can be configured independently.
//!  The \e ulMClock parameter is chosen from the following:
//!
//! - one of \b I2S_TX_MCLK_EXT or \b I2S_TX_MCLK_INT
//! - one of \b I2S_RX_MCLK_EXT or \b I2S_RX_MCLK_INT
//!
//! \return Returns None.
//
//*****************************************************************************
void
I2SMasterClockSelect(unsigned long ulBase, unsigned long ulMClock)
{
    unsigned long ulConfig;

    //
    // Check the arguments.
    //
    ASSERT(ulBase == I2S0_BASE);
    ASSERT((ulMClock & (I2S_TX_MCLK_EXT | I2S_RX_MCLK_EXT)) == ulMClock);

    //
    // Set the clock selection bits in the configuation word.
    //
    ulConfig = HWREG(ulBase + I2S_O_CFG) &
                   ~(I2S_TX_MCLK_EXT | I2S_RX_MCLK_EXT);
    HWREG(ulBase + I2S_O_CFG) = ulConfig | ulMClock;
}

//*****************************************************************************
//
//! Enables I2S interrupt sources.
//!
//! \param ulBase is the I2S module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
//!
//! This function enables the specified I2S sources to generate interrupts.
//! The \e ulIntFlags parameter can be the logical OR of any of the following
//! values:
//!
//! - \b I2S_INT_RXERR for receive errors
//! - \b I2S_INT_RXREQ for receive FIFO service requests
//! - \b I2S_INT_TXERR for transmit errors
//! - \b I2S_INT_TXREQ for transmit FIFO service requests
//!
//! \return Returns None.
//
//*****************************************************************************
void
I2SIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == I2S0_BASE);
    ASSERT((ulIntFlags & (I2S_INT_RXERR | I2S_INT_RXREQ |
                          I2S_INT_TXERR | I2S_INT_TXREQ)) == ulIntFlags);

    //
    // Enable the specified interrupts.
    //
    HWREG(ulBase + I2S_O_IM) |= ulIntFlags;
}

//*****************************************************************************
//
//! Disables I2S interrupt sources.
//!
//! \param ulBase is the I2S module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
//!
//! This function disables the specified I2S sources for interrupt
//! generation.  The \e ulIntFlags parameter can be the logical OR
//! of any of the following values: \b I2S_INT_RXERR, \b I2S_INT_RXREQ,
//! \b I2S_INT_TXERR, or \b I2S_INT_TXREQ.
//!
//! \return Returns None.
//
//*****************************************************************************
void
I2SIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == I2S0_BASE);
    ASSERT((ulIntFlags & (I2S_INT_RXERR | I2S_INT_RXREQ |
                          I2S_INT_TXERR | I2S_INT_TXREQ)) == ulIntFlags);

    //
    // Enable the specified interrupts.
    //
    HWREG(ulBase + I2S_O_IM) &= ~ulIntFlags;
}

//*****************************************************************************
//
//! Gets the I2S interrupt status.
//!
//! \param ulBase is the I2S module base address.
//! \param bMasked is set \b true to get the masked interrupt status, or
//! \b false to get the raw interrupt status.
//!
//! This function returns the I2S interrupt status.  It can return either
//! the raw or masked interrupt status.
//!
//! \return Returns the masked or raw I2S interrupt status, as a bit field
//! of any of the following values: \b I2S_INT_RXERR, \b I2S_INT_RXREQ,
//! \b I2S_INT_TXERR, or \b I2S_INT_TXREQ
//
//*****************************************************************************
unsigned long
I2SIntStatus(unsigned long ulBase, tBoolean bMasked)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == I2S0_BASE);

    //
    // Return either the interrupt status or the raw interrupt status as
    // requested.
    //
    if(bMasked)
    {
        return(HWREG(ulBase + I2S_O_MIS));
    }
    else
    {
        return(HWREG(ulBase + I2S_O_RIS));
    }
}

//*****************************************************************************
//
//! Clears pending I2S interrupt sources.
//!
//! \param ulBase is the I2S module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
//!
//! This function clears the specified pending I2S interrupts.  This must
//! be done in the interrupt handler to keep the handler from being called
//! again immediately upon exit.  The \e ulIntFlags parameter can be the
//! logical OR of any of the following values: \b I2S_INT_RXERR,
//! \b I2S_INT_RXREQ, \b I2S_INT_TXERR, or \b I2S_INT_TXREQ.
//!
//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
//! several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared.  Failure to do so may result in the interrupt handler
//! being immediately reentered (since NVIC still sees the interrupt source
//! asserted).
//!
//! \return Returns None.
//
//*****************************************************************************
void
I2SIntClear(unsigned long ulBase, unsigned long ulIntFlags)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == I2S0_BASE);
    ASSERT((ulIntFlags & (I2S_INT_RXERR | I2S_INT_RXREQ |
                          I2S_INT_TXERR | I2S_INT_TXREQ)) == ulIntFlags);

    //
    // Clear the requested interrupt sources.
    //
    HWREG(ulBase + I2S_O_IC) = ulIntFlags;
}

//*****************************************************************************
//
//! Registers an interrupt handler for the I2S controller.
//!
//! \param ulBase is the I2S module base address.
//! \param pfnHandler is a pointer to the function to be called when the
//! interrupt is activated.
//!
//! This sets and enables the handler to be called when the I2S controller
//! generates an interrupt.  Specific I2S interrupts must still be enabled
//! with the I2SIntEnable() function.  It is the responsibility of the
//! interrupt handler to clear any pending interrupts with I2SIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == I2S0_BASE);
    ASSERT(pfnHandler);

    //
    // Register the interrupt handler.
    //
    IntRegister(INT_I2S0, pfnHandler);

    //
    // Enable the I2S interface interrupt.
    //
    IntEnable(INT_I2S0);
}

//*****************************************************************************
//
//! Unregisters an interrupt handler for the I2S controller.
//!
//! \param ulBase is the I2S module base address.
//!
//! This function will disable and clear the handler to be called when the
//! I2S interrupt occurs.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
I2SIntUnregister(unsigned long ulBase)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == I2S0_BASE);

    //
    // Disable the I2S interface interrupt.
    //
    IntDisable(INT_I2S0);

    //
    // Unregister the interrupt handler.
    //
    IntUnregister(INT_I2S0);
}

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************