i2s.c

基于TI公司Cortex-M3的uart超级通信开发

    //
    // Read and return the transmit FIFO level.
    //
    return(HWREG(ulBase + I2S_O_TXLEV));
}

//*****************************************************************************
//
//! Enables the I2S receive module for operation.
//!
//! \param ulBase is the I2S module base address.
//!
//! This function enables the receive module for operation.  The module
//! should be enabled after configuration.  When the module is disabled,
//! no data will be clocked in regardless of the signals on the I2S interface.
//!
//! \return None.
//
//*****************************************************************************
void
I2SRxEnable(unsigned long ulBase)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == I2S0_BASE);

    //
    // Enable the tx FIFO service request.
    //
    HWREG(ulBase + I2S_O_RXISM) = I2S_RXISM_FFM;

    //
    // Read-modify-write the enable bit.
    //
    HWREG(ulBase + I2S_O_CFG) |= I2S_CFG_RXEN;
}

//*****************************************************************************
//
//! Disables the I2S receive module for operation.
//!
//! \param ulBase is the I2S module base address.
//!
//! This function disables the receive module for operation.  The module
//! should be disabled before configuration.  When the module is disabled,
//! no data will be clocked in regardless of the signals on the I2S interface.
//!
//! \return None.
//
//*****************************************************************************
void
I2SRxDisable(unsigned long ulBase)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == I2S0_BASE);

    //
    // Read-modify-write the enable bit.
    //
    HWREG(ulBase + I2S_O_CFG) &= ~I2S_CFG_RXEN;
}

//*****************************************************************************
//
//! Reads data samples from the I2S receive FIFO with blocking.
//!
//! \param ulBase is the I2S module base address.
//! \param pulData points to storage for the returned I2S sample data.
//!
//! This function reads a single channel sample or combined left-right
//! samples from the I2S receive FIFO.  The format of the sample is determined
//! by the configuration that was used with the function I2SRxConfigSet().
//! If the receive mode is I2S_MODE_DUAL_STEREO then the returned value
//! contains either the left or right sample.  The left and right sample
//! alternate with each read from the FIFO, left sample first.  If the receive
//! mode is I2S_MODE_COMPACT_STEREO_16 or I2S_MODE_COMPACT_STEREO_8, then the
//! returned data contains both the left and right samples.  If the
//! receive mode is I2S_MODE_SINGLE_MONO then the returned data
//! contains the single channel sample.
//!
//! For the compact modes, both the left and right samples are read at
//! the same time.  If 16-bit compact mode is used, then the least significant
//! 16 bits contain the left sample, and the most significant 16 bits contain
//! the right sample.  If 8-bit compact mode is used, then the lower 8 bits
//! contain the left sample, and the next 8 bits contain the right sample,
//! with the upper 16 bits unused.
//!
//! If there is no data in the receive FIFO, then this function will wait
//! in a polling loop until data is available.
//!
//! \return None.
//
//*****************************************************************************
void
I2SRxDataGet(unsigned long ulBase, unsigned long *pulData)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == I2S0_BASE);

    //
    // Wait until there is data available.
    //
    while(HWREG(ulBase + I2S_O_RXLEV) == 0)
    {
    }

    //
    // Read data from the I2S receive FIFO.
    //
    *pulData = HWREG(ulBase + I2S_O_RXFIFO);
}

//*****************************************************************************
//
//! Reads data samples from the I2S receive FIFO without blocking.
//!
//! \param ulBase is the I2S module base address.
//! \param pulData points to storage for the returned I2S sample data.
//!
//! This function reads a single channel sample or combined left-right
//! samples from the I2S receive FIFO.  The format of the sample is determined
//! by the configuration that was used with the function I2SRxConfigSet().
//! If the receive mode is I2S_MODE_DUAL_STEREO then the received data
//! contains either the left or right sample.  The left and right sample
//! alternate with each read from the FIFO, left sample first.  If the receive
//! mode is I2S_MODE_COMPACT_STEREO_16 or I2S_MODE_COMPACT_STEREO_8, then the
//! received data contains both the left and right samples.  If the
//! receive mode is I2S_MODE_SINGLE_MONO then the received data
//! contains the single channel sample.
//!
//! For the compact modes, both the left and right samples are read at
//! the same time.  If 16-bit compact mode is used, then the least significant
//! 16 bits contain the left sample, and the most significant 16 bits contain
//! the right sample.  If 8-bit compact mode is used, then the lower 8 bits
//! contain the left sample, and the next 8 bits contain the right sample,
//! with the upper 16 bits unused.
//!
//! If there is no data in the receive FIFO, then this function will return
//! immediately without reading any data from the FIFO.
//!
//! \return The number of elements read from the I2S receive FIFO (1 or 0).
//
//*****************************************************************************
long
I2SRxDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == I2S0_BASE);

    //
    // Check for available samples.
    //
    if(HWREG(ulBase + I2S_O_RXLEV) != 0)
    {
        *pulData = HWREG(ulBase + I2S_O_RXFIFO);
        return(1);
    }
    else
    {
        return(0);
    }
}

//*****************************************************************************
//
//! Configures the I2S receive module.
//!
//! \param ulBase is the I2S module base address.
//! \param ulConfig is the logical OR of the configuration options.
//!
//! This function is used to configure the options for the I2S receive
//! channel.  The parameter \e ulConfig is the logical OR of the following
//! options:
//!
//! - \b I2S_CONFIG_FORMAT_I2S for standard I2S format,
//! \b I2S_CONFIG_FORMAT_LEFT_JUST for left justified format, or
//! \b I2S_CONFIG_FORMAT_RIGHT_JUST for right justified format.
//! - \b I2S_CONFIG_SCLK_INVERT to invert the polarity of the serial bit clock.
//! - \b I2S_CONFIG_MODE_DUAL for dual channel stereo,
//! \b I2S_CONFIG_MODE_COMPACT_16 for 16-bit compact stereo mode,
//! \b I2S_CONFIG_MODE_COMPACT_8 for 8-bit compact stereo mode, or
//! \b I2S_CONFIG_MODE_MONO for single channel mono format.
//! - \b I2S_CONFIG_CLK_MASTER or \b I2S_CONFIG_CLK_SLAVE to select whether
//! the I2S receiver is the clock master or slave.
//! - \b I2S_CONFIG_SAMPLE_SIZE_32, \b _24, \b _20, \b _16, or \b _8
//! to select the number of bits per sample.
//! - \b I2S_CONFIG_WIRE_SIZE_32, \b _24, \b _20, \b _16, or \b _8
//! to select the number of bits per word that are transferred on the data
//! line.
//!
//! \return None.
//
//*****************************************************************************
void
I2SRxConfigSet(unsigned long ulBase, unsigned long ulConfig)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == I2S0_BASE);
    ASSERT((ulConfig & (I2S_CONFIG_FORMAT_MASK | I2S_CONFIG_MODE_MASK |
                        I2S_CONFIG_CLK_MASK | I2S_CONFIG_SAMPLE_SIZE_MASK |
                        I2S_CONFIG_WIRE_SIZE_MASK)) == ulConfig);

    //
    // Clear out any prior config of the RX FIFO config register.
    //
    HWREG(ulBase + I2S_O_RXFIFOCFG) = 0;

    //
    // If mono mode is used, then the FMM bit needs to be set.
    //
    if((ulConfig & I2S_CONFIG_MODE_MASK) == I2S_CONFIG_MODE_MONO)
    {
        HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_FMM;
    }

    //
    // If a compact mode is used, then the CSS bit needs to be set.
    //
    else if((ulConfig & I2S_CONFIG_MODE_MASK) == I2S_CONFIG_MODE_COMPACT_8)
    {
        HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_CSS;
    }

    //
    // The "mono" bits needs to be removed from the configuration word
    // prior to writing to hardware, because the RX configuration register
    // does not actually use these bits.
    //
    ulConfig &= ~I2S_CONFIG_MODE_MONO;

    //
    // Write the configuration register.  Since all the fields are
    // specified by the configuration parameter, it is not necessary
    // to do a read-modify-write.
    //
    HWREG(ulBase + I2S_O_RXCFG) = ulConfig;
}

//*****************************************************************************
//
//! Sets the FIFO level at which a service request is generated.
//!
//! \param ulBase is the I2S module base address.
//! \param ulLevel is the FIFO service request limit.
//!
//! This function is used to set the receive FIFO fullness level at which
//! a service request will occur.  The service request is used to generate
//! an interrupt or a DMA transfer request.  The receive FIFO will
//! generate a service request when the number of items in the FIFO is
//! greater than the level specified in the \e ulLevel parameter.  For example,
//! if \e ulLevel is 4, then a service request will be generated when
//! there are more than 4 samples available in the receive FIFO.
//!
//! For the purposes of counting the FIFO level, a left-right sample pair
//! counts as 2, whether the mode is dual or compact stereo.  When mono
//! mode is used, internally the mono sample is still treated as a sample
//! pair, so a single mono sample counts as 2.  Since the FIFO always deals
//! with sample pairs, the level must be an even number from 0 to 16.  The
//! minimum value is 0, which will cause a service request when there
//! is any data available in the FIFO.  The maximum value is 16, which
//! disables the service request (because there cannot be more than 16
//! items in the FIFO).
//!
//! \return None.
//
//*****************************************************************************
void
I2SRxFIFOLimitSet(unsigned long ulBase, unsigned long ulLevel)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == I2S0_BASE);
    ASSERT(ulLevel <= 16);

    //
    // Write the FIFO limit
    //
    HWREG(ulBase + I2S_O_RXLIMIT) = ulLevel;
}

//*****************************************************************************
//
//! Gets the current setting of the FIFO service request level.
//!
//! \param ulBase is the I2S module base address.
//!
//! This function is used to get the value of the receive FIFO service
//! request level.  This value is set using the I2SRxFIFOLimitSet()
//! function.
//!
//! \return Returns the current value of the FIFO service request limit.
//
//*****************************************************************************
unsigned long
I2SRxFIFOLimitGet(unsigned long ulBase)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == I2S0_BASE);

    //
    // Read and return the FIFO limit.  The lower bit is masked
    // because it always reads as 1, and has no meaning.
    //
    return(HWREG(ulBase + I2S_O_RXLIMIT) & 0xFFFE);
}

//*****************************************************************************
//
//! Gets the number of samples in the receive FIFO.
//!
//! \param ulBase is the I2S module base address.
//!
//! This function is used to get the number of samples in the receive
//! FIFO.  For the purposes of measuring the FIFO level, a left-right sample
//! pair counts as 2, whether the mode is dual or compact stereo.  When mono
//! mode is used, internally the mono sample is still treated as a sample
//! pair, so a single mono sample counts as 2.  Since the FIFO always deals
//! with sample pairs, normally the level will be an even number from 0 to
//! 16.  If dual stereo mode is used and only the left sample has been
//! read without reading the matching right sample, then the FIFO level will
//! be an odd value.  If the FIFO level is odd, it indicates a left-right
//! sample mismatch.
//!
//! \return Returns the number of samples in the transmit FIFO, which will
//! normally be an even number.
//
//*****************************************************************************
unsigned long
I2SRxFIFOLevelGet(unsigned long ulBase)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == I2S0_BASE);

    //
    // Read and return the receive FIFO level.
    //
    return(HWREG(ulBase + I2S_O_RXLEV));
}

//*****************************************************************************
//
//! Enables the I2S transmit and receive modules for operation.
//!
//! \param ulBase is the I2S module base address.
//!
//! This function simultaneously enables the transmit and receive modules for
//! operation, providing a synchronized SCLK and LRCLK.  The module should be
//! enabled after configuration.  When the module is disabled, no data or
//! clocks will be generated on the I2S signals.
//!
//! \return None.
//
//*****************************************************************************
void
I2STxRxEnable(unsigned long ulBase)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == I2S0_BASE);

    //
    // Enable the Tx FIFO service request.
    //
    HWREG(ulBase + I2S_O_TXISM) = I2S_TXISM_FFM;