epi.c

基于TI公司Cortex-M3的uart超级通信开发

//! \param ulCount is the maximum count of items to read.
//! \param pucBuf is the caller supplied buffer where the read data should
//! be stored.
//!
//! This function reads 8-bit data items from the read FIFO and stores
//! the values in a caller supplied buffer.  The function will read and store
//! data from the FIFO until there is no more data in the FIFO or the maximum
//! count is reached as specified in the parameter \e ulCount.  The actual
//! count of items will be returned.
//!
//! \return The number of items read from the FIFO.
//
//*****************************************************************************
unsigned long
EPINonBlockingReadGet8(unsigned long ulBase, unsigned long ulCount,
                       unsigned char *pucBuf)
{
    unsigned long ulCountRead = 0;

    //
    // Check the arguments.
    //
    ASSERT(ulBase == EPI0_BASE);
    ASSERT(ulCount < 4096);
    ASSERT(pucBuf);

    //
    // Read from the FIFO while there are any items to read, and
    // the callers specified count is not exceeded.
    //
    while(HWREG(ulBase + EPI_O_RFIFOCNT) && ulCount--)
    {
        //
        // Read from the FIFO and store in the caller supplied buffer.
        //
        *pucBuf = (unsigned char)HWREG(ulBase + EPI_O_READFIFO);

        //
        // Update the caller's buffer pointer and the count of items read.
        //
        pucBuf++;
        ulCountRead++;
    }

    //
    // Return the count of items read to the caller.
    //
    return(ulCountRead);
}

//*****************************************************************************
//
//! Configures the read FIFO.
//!
//! \param ulBase is the EPI module base address.
//! \param ulConfig is the FIFO configuration.
//!
//! This function configures the FIFO trigger levels and error
//! generation.  The parameter \e ulConfig is the logical OR of the
//! following:
//!
//! - \b EPI_FIFO_CONFIG_WTFULLERR - enables an error interrupt when a write is
//! attempted and the write FIFO is full
//! - \b EPI_FIFO_CONFIG_RSTALLERR - enables an error interrupt when a read is
//! stalled due to an interleaved write or other reason
//! - \b EPI_FIFO_CONFIG_TX_EMPTY, \b EPI_FIFO_CONFIG_TX_1_4,
//! \b EPI_FIFO_CONFIG_TX_1_2, or \b EPI_FIFO_CONFIG_TX_3_4 to set the
//! TX FIFO trigger level to empty, 1/4, 1/2, or 3/4 level
//! - \b EPI_FIFO_CONFIG_RX_1_8, \b EPI_FIFO_CONFIG_RX_1_4,
//! \b EPI_FIFO_CONFIG_RX_1_2, \b EPI_FIFO_CONFIG_RX_3_4,
//! \b EPI_FIFO_CONFIG_RX_7_8, or \b EPI_FIFO_CONFIG_RX_FULL to set the
//! RX FIFO trigger level to 1/8, 1/4, 1/2, 3/4, 7/8 or full level
//!
//! \return None.
//
//*****************************************************************************
void
EPIFIFOConfig(unsigned long ulBase, unsigned long ulConfig)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == EPI0_BASE);
    ASSERT(ulConfig == (ulConfig & 0x00030077));

    //
    // Load the configuration into the FIFO config reg.
    //
    HWREG(ulBase + EPI_O_FIFOLVL) = ulConfig;
}

//*****************************************************************************
//
//! Reads the number of empty slots in the write transaction FIFO.
//!
//! \param ulBase is the EPI module base address.
//!
//! This function returns the number of slots available in the transaction
//! FIFO.  It can be used in a polling method to avoid attempting a write
//! that would stall.
//!
//! \return The number of empty slots in the transaction FIFO.
//
//*****************************************************************************
unsigned long
EPIWriteFIFOCountGet(unsigned long ulBase)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == EPI0_BASE);

    //
    // Read the FIFO count and return it to the caller.
    //
    return(HWREG(ulBase + EPI_O_WFIFOCNT));
}

//*****************************************************************************
//
//! Enables EPI interrupt sources.
//!
//! \param ulBase is the EPI module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
//!
//! This function enables the specified EPI sources to generate interrupts.
//! The \e ulIntFlags parameter can be the logical OR of any of the following
//! values:
//!
//! - \b EPI_INT_TXREQ - transmit FIFO is below the trigger level
//! - \b EPI_INT_RXREQ - read FIFO is above the trigger level
//! - \b EPI_INT_ERR - an error condition occurred
//!
//! \return Returns None.
//
//*****************************************************************************
void
EPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == EPI0_BASE);
    ASSERT(ulIntFlags < 16);

    //
    // Write the interrupt flags mask to the mask register.
    //
    HWREG(ulBase + EPI_O_IM) |= ulIntFlags;
}

//*****************************************************************************
//
//! Disables EPI interrupt sources.
//!
//! \param ulBase is the EPI module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
//!
//! This function disables the specified EPI sources for interrupt
//! generation.  The \e ulIntFlags parameter can be the logical OR
//! of any of the following values: \b EPI_INT_RXREQ, \b EPI_INT_TXREQ, or
//! \b I2S_INT_ERR.
//!
//! \return Returns None.
//
//*****************************************************************************
void
EPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == EPI0_BASE);
    ASSERT(ulIntFlags < 16);

    //
    // Write the interrupt flags mask to the mask register.
    //
    HWREG(ulBase + EPI_O_IM) &= ~ulIntFlags;
}

//*****************************************************************************
//
//! Gets the EPI interrupt status.
//!
//! \param ulBase is the EPI module base address.
//! \param bMasked is set \b true to get the masked interrupt status, or
//! \b false to get the raw interrupt status.
//!
//! This function returns the EPI interrupt status.  It can return either
//! the raw or masked interrupt status.
//!
//! \return Returns the masked or raw EPI interrupt status, as a bit field
//! of any of the following values: \b EPI_INT_TXREQ, \b EPI_INT_RXREQ,
//! or \b EPI_INT_ERR
//
//*****************************************************************************
unsigned long
EPIIntStatus(unsigned long ulBase, tBoolean bMasked)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == EPI0_BASE);

    //
    // Return either the interrupt status or the raw interrupt status as
    // requested.
    //
    if(bMasked)
    {
        return(HWREG(ulBase + EPI_O_MIS));
    }
    else
    {
        return(HWREG(ulBase + EPI_O_RIS));
    }
}

//*****************************************************************************
//
//! Gets the EPI error interrupt status.
//!
//! \param ulBase is the EPI module base address.
//!
//! This function returns the error status of the EPI.  If the return value of
//! the function EPIIntStatus() has the flag \b EPI_INT_ERR set, then this
//! function can be used to determine the cause of the error.
//!
//! This function returns a bit mask of error flags, which can be the logical
//! OR of any of the following:
//!
//! - \b EPI_INT_ERR_WTFULL - occurs when a write stalled when the transaction
//! FIFO was full
//! - \b EPI_INT_ERR_RSTALL - occurs when a read stalled
//! - \b EPI_INT_ERR_TIMEOUT - occurs when the external clock enable held
//! off a transaction longer than the configured maximum wait time
//!
//! \return Returns the interrupt error flags as the logical OR of any of
//! the following: \b EPI_INT_ERR_WTFULL, \b EPI_INT_ERR_RSTALL, or
//! \b EPI_INT_ERR_TIMEOUT.
//
//*****************************************************************************
unsigned long
EPIIntErrorStatus(unsigned long ulBase)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == EPI0_BASE);

    //
    // Read the error status and return to caller.
    //
    return(HWREG(ulBase + EPI_O_EISC));
}

//*****************************************************************************
//
//! Clears pending EPI error sources.
//!
//! \param ulBase is the EPI module base address.
//! \param ulErrFlags is a bit mask of the error sources to be cleared.
//!
//! This function clears the specified pending EPI errors.  The \e ulErrFlags
//! parameter can be the logical OR of any of the following values:
//! \b EPI_INT_ERR_WTFULL, \b EPI_INT_ERR_RSTALL, or \b EPI_INT_ERR_TIMEOUT.
//!
//! \return Returns None.
//
//*****************************************************************************
void
EPIIntErrorClear(unsigned long ulBase, unsigned long ulErrFlags)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == EPI0_BASE);
    ASSERT(ulErrFlags < 16);

    //
    // Write the error flags to the register to clear the pending errors.
    //
    HWREG(ulBase + EPI_O_EISC) = ulErrFlags;
}

//*****************************************************************************
//
//! Registers an interrupt handler for the EPI module.
//!
//! \param ulBase is the EPI module base address.
//! \param pfnHandler is a pointer to the function to be called when the
//! interrupt is activated.
//!
//! This sets and enables the handler to be called when the EPI module
//! generates an interrupt.  Specific EPI interrupts must still be enabled
//! with the EPIIntEnable() function.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
EPIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == EPI0_BASE);
    ASSERT(pfnHandler);

    //
    // Register the interrupt handler.
    //
    IntRegister(INT_EPI0, pfnHandler);

    //
    // Enable the EPI interface interrupt.
    //
    IntEnable(INT_EPI0);
}

//*****************************************************************************
//
//! Unregisters an interrupt handler for the EPI module.
//!
//! \param ulBase is the EPI module base address.
//!
//! This function will disable and clear the handler to be called when the
//! EPI interrupt occurs.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
EPIIntUnregister(unsigned long ulBase)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == EPI0_BASE);

    //
    // Disable the EPI interface interrupt.
    //
    IntDisable(INT_EPI0);

    //
    // Unregister the interrupt handler.
    //
    IntUnregister(INT_EPI0);
}

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************