hw_can.h

基于TI公司Cortex-M3的uart超级通信开发

//*****************************************************************************
//
// hw_can.h - Defines and macros used when accessing the CAN controllers.
//
// Copyright (c) 2006-2009 Luminary Micro, Inc.  All rights reserved.
// Software License Agreement
// 
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
// 
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws.  All rights are reserved.  You may not combine
// this software with "viral" open-source software in order to form a larger
// program.  Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
// 
// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
// 
// This is part of revision 5228 of the Stellaris Firmware Development Package.
//
//*****************************************************************************

#ifndef __HW_CAN_H__
#define __HW_CAN_H__

//*****************************************************************************
//
// The following are defines for the CAN register offsets.
//
//*****************************************************************************
#define CAN_O_CTL               0x00000000  // Control register
#define CAN_O_STS               0x00000004  // Status register
#define CAN_O_ERR               0x00000008  // Error register
#define CAN_O_BIT               0x0000000C  // Bit Timing register
#define CAN_O_INT               0x00000010  // Interrupt register
#define CAN_O_TST               0x00000014  // Test register
#define CAN_O_BRPE              0x00000018  // Baud Rate Prescaler register
#define CAN_O_IF1CRQ            0x00000020  // Interface 1 Command Request reg
#define CAN_O_IF1CMSK           0x00000024  // Interface 1 Command Mask reg
#define CAN_O_IF1MSK1           0x00000028  // Interface 1 Mask 1 register
#define CAN_O_IF1MSK2           0x0000002C  // Interface 1 Mask 2 register
#define CAN_O_IF1ARB1           0x00000030  // Interface 1 Arbitration 1 reg
#define CAN_O_IF1ARB2           0x00000034  // Interface 1 Arbitration 2 reg
#define CAN_O_IF1MCTL           0x00000038  // Interface 1 Message Control reg
#define CAN_O_IF1DA1            0x0000003C  // Interface 1 DataA 1 register
#define CAN_O_IF1DA2            0x00000040  // Interface 1 DataA 2 register
#define CAN_O_IF1DB1            0x00000044  // Interface 1 DataB 1 register
#define CAN_O_IF1DB2            0x00000048  // Interface 1 DataB 2 register
#define CAN_O_IF2CRQ            0x00000080  // Interface 2 Command Request reg
#define CAN_O_IF2CMSK           0x00000084  // Interface 2 Command Mask reg
#define CAN_O_IF2MSK1           0x00000088  // Interface 2 Mask 1 register
#define CAN_O_IF2MSK2           0x0000008C  // Interface 2 Mask 2 register
#define CAN_O_IF2ARB1           0x00000090  // Interface 2 Arbitration 1 reg
#define CAN_O_IF2ARB2           0x00000094  // Interface 2 Arbitration 2 reg
#define CAN_O_IF2MCTL           0x00000098  // Interface 2 Message Control reg
#define CAN_O_IF2DA1            0x0000009C  // Interface 2 DataA 1 register
#define CAN_O_IF2DA2            0x000000A0  // Interface 2 DataA 2 register
#define CAN_O_IF2DB1            0x000000A4  // Interface 2 DataB 1 register
#define CAN_O_IF2DB2            0x000000A8  // Interface 2 DataB 2 register
#define CAN_O_TXRQ1             0x00000100  // Transmission Request 1 register
#define CAN_O_TXRQ2             0x00000104  // Transmission Request 2 register
#define CAN_O_NWDA1             0x00000120  // New Data 1 register
#define CAN_O_NWDA2             0x00000124  // New Data 2 register
#define CAN_O_MSG1INT           0x00000140  // CAN Message 1 Interrupt Pending
#define CAN_O_MSG2INT           0x00000144  // CAN Message 2 Interrupt Pending
#define CAN_O_MSG1VAL           0x00000160  // CAN Message 1 Valid
#define CAN_O_MSG2VAL           0x00000164  // CAN Message 2 Valid

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_CTL register.
//
//*****************************************************************************
#define CAN_CTL_TEST            0x00000080  // Test mode enable
#define CAN_CTL_CCE             0x00000040  // Configuration change enable
#define CAN_CTL_DAR             0x00000020  // Disable automatic retransmission
#define CAN_CTL_EIE             0x00000008  // Error interrupt enable
#define CAN_CTL_SIE             0x00000004  // Status change interrupt enable
#define CAN_CTL_IE              0x00000002  // Module interrupt enable
#define CAN_CTL_INIT            0x00000001  // Initialization

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_STS register.
//
//*****************************************************************************
#define CAN_STS_BOFF            0x00000080  // Bus Off status
#define CAN_STS_EWARN           0x00000040  // Error Warning status
#define CAN_STS_EPASS           0x00000020  // Error Passive status
#define CAN_STS_RXOK            0x00000010  // Received Message Successful
#define CAN_STS_TXOK            0x00000008  // Transmitted Message Successful
#define CAN_STS_LEC_M           0x00000007  // Last Error Code
#define CAN_STS_LEC_NONE        0x00000000  // No error
#define CAN_STS_LEC_STUFF       0x00000001  // Stuff error
#define CAN_STS_LEC_FORM        0x00000002  // Form(at) error
#define CAN_STS_LEC_ACK         0x00000003  // Ack error
#define CAN_STS_LEC_BIT1        0x00000004  // Bit 1 error
#define CAN_STS_LEC_BIT0        0x00000005  // Bit 0 error
#define CAN_STS_LEC_CRC         0x00000006  // CRC error
#define CAN_STS_LEC_NOEVENT     0x00000007  // Unused

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_ERR register.
//
//*****************************************************************************
#define CAN_ERR_RP              0x00008000  // Receive error passive status
#define CAN_ERR_REC_M           0x00007F00  // Receive Error Counter
#define CAN_ERR_TEC_M           0x000000FF  // Transmit Error Counter
#define CAN_ERR_REC_S           8           // Receive error counter bit pos
#define CAN_ERR_TEC_S           0           // Transmit error counter bit pos

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_BIT register.
//
//*****************************************************************************
#define CAN_BIT_TSEG2_M         0x00007000  // Time Segment after Sample Point
#define CAN_BIT_TSEG1_M         0x00000F00  // Time Segment Before Sample Point
#define CAN_BIT_SJW_M           0x000000C0  // (Re)Synchronization Jump Width
#define CAN_BIT_BRP_M           0x0000003F  // Baud Rate Prescalar
#define CAN_BIT_TSEG2_S         12
#define CAN_BIT_TSEG1_S         8
#define CAN_BIT_SJW_S           6
#define CAN_BIT_BRP_S           0

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_INT register.
//
//*****************************************************************************
#define CAN_INT_INTID_M         0x0000FFFF  // Interrupt Identifier
#define CAN_INT_INTID_NONE      0x00000000  // No Interrupt Pending
#define CAN_INT_INTID_STATUS    0x00008000  // Status Interrupt

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_TST register.
//
//*****************************************************************************
#define CAN_TST_RX              0x00000080  // CAN_RX pin status
#define CAN_TST_TX_M            0x00000060  // Overide control of CAN_TX pin
#define CAN_TST_TX_CANCTL       0x00000000  // CAN core controls CAN_TX
#define CAN_TST_TX_SAMPLE       0x00000020  // Sample Point on CAN_TX
#define CAN_TST_TX_DOMINANT     0x00000040  // Dominant value on CAN_TX
#define CAN_TST_TX_RECESSIVE    0x00000060  // Recessive value on CAN_TX
#define CAN_TST_LBACK           0x00000010  // Loop back mode
#define CAN_TST_SILENT          0x00000008  // Silent mode
#define CAN_TST_BASIC           0x00000004  // Basic mode

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_BRPE register.
//
//*****************************************************************************
#define CAN_BRPE_BRPE_M         0x0000000F  // Baud Rate Prescalar Extension
#define CAN_BRPE_BRPE_S         0

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1CRQ register.
//
//*****************************************************************************
#define CAN_IF1CRQ_BUSY         0x00008000  // Busy Flag
#define CAN_IF1CRQ_MNUM_M       0x0000003F  // Message Number
#define CAN_IF1CRQ_MNUM_RSVD    0x00000000  // 0 is not a valid message number;
                                            // it is interpreted as 0x20, or
                                            // object 32

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1CMSK register.
//
//*****************************************************************************
#define CAN_IF1CMSK_WRNRD       0x00000080  // Write, Not Read
#define CAN_IF1CMSK_MASK        0x00000040  // Access Mask Bits
#define CAN_IF1CMSK_ARB         0x00000020  // Access Arbitration Bits
#define CAN_IF1CMSK_CONTROL     0x00000010  // Access Control Bits
#define CAN_IF1CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit
#define CAN_IF1CMSK_NEWDAT      0x00000004  // Access New Data
#define CAN_IF1CMSK_TXRQST      0x00000004  // Access Transmission Request
#define CAN_IF1CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3
#define CAN_IF1CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
//
//*****************************************************************************
#define CAN_IF1MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask
#define CAN_IF1MSK1_IDMSK_S     0

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1MSK2 register.
//
//*****************************************************************************
#define CAN_IF1MSK2_MXTD        0x00008000  // Mask Extended Identifier
#define CAN_IF1MSK2_MDIR        0x00004000  // Mask Message Direction
#define CAN_IF1MSK2_IDMSK_M     0x00001FFF  // Identifier Mask
#define CAN_IF1MSK2_IDMSK_S     0

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
//
//*****************************************************************************
#define CAN_IF1ARB1_ID_M        0x0000FFFF  // Message Identifier
#define CAN_IF1ARB1_ID_S        0

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1ARB2 register.
//
//*****************************************************************************
#define CAN_IF1ARB2_MSGVAL      0x00008000  // Message Valid
#define CAN_IF1ARB2_XTD         0x00004000  // Extended Identifier
#define CAN_IF1ARB2_DIR         0x00002000  // Message Direction
#define CAN_IF1ARB2_ID_M        0x00001FFF  // Message Identifier
#define CAN_IF1ARB2_ID_S        0

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1MCTL register.
//
//*****************************************************************************
#define CAN_IF1MCTL_NEWDAT      0x00008000  // New Data
#define CAN_IF1MCTL_MSGLST      0x00004000  // Message Lost
#define CAN_IF1MCTL_INTPND      0x00002000  // Interrupt Pending
#define CAN_IF1MCTL_UMASK       0x00001000  // Use Acceptance Mask
#define CAN_IF1MCTL_TXIE        0x00000800  // Transmit Interrupt Enable
#define CAN_IF1MCTL_RXIE        0x00000400  // Receive Interrupt Enable
#define CAN_IF1MCTL_RMTEN       0x00000200  // Remote Enable
#define CAN_IF1MCTL_TXRQST      0x00000100  // Transmit Request
#define CAN_IF1MCTL_EOB         0x00000080  // End of Buffer
#define CAN_IF1MCTL_DLC_M       0x0000000F  // Data Length Code
#define CAN_IF1MCTL_DLC_S       0

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1DA1 register.
//
//*****************************************************************************
#define CAN_IF1DA1_DATA_M       0x0000FFFF  // Data
#define CAN_IF1DA1_DATA_S       0

//*****************************************************************************