📄 hw_sysctl.h
字号:
#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7
#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8
#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9
#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10
#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11
#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12
#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13
#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14
#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15
#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16
#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17
#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18
#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19
#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20
#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21
#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22
#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23
#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24
#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25
#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26
#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27
#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28
#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29
#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30
#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31
#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32
#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33
#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34
#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35
#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36
#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37
#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38
#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39
#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40
#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41
#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42
#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43
#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44
#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45
#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46
#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47
#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48
#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49
#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50
#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51
#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52
#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53
#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54
#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55
#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56
#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57
#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58
#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59
#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60
#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61
#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62
#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63
#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64
#define SYSCTL_RCC2_FRACT 0x00400000 // Fractional divide
#define SYSCTL_RCC2_USBPWRDN 0x00004000 // Power-Down USB PLL
#define SYSCTL_RCC2_PWRDN2 0x00002000 // PLL power down
#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL bypass
#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // System Clock Source
#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // Use the main oscillator
#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // Use the internal oscillator
#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // Use the internal oscillator / 4
#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // Use the 30 KHz internal osc
#define SYSCTL_RCC2_OSCSRC2_419 0x00000060 // Use the 4.19 MHz external osc
#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // Use the 32 KHz external osc
#define SYSCTL_RCC2_SYSDIV2_S 23 // Shift to the SYSDIV2 field
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_MOSCCTL register.
//
//*****************************************************************************
#define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_RCGC0 register.
//
//*****************************************************************************
#define SYSCTL_RCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control
#define SYSCTL_RCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control
#define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control
#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control
#define SYSCTL_RCGC0_PWM 0x00100000 // PWM Clock Gating Control
#define SYSCTL_RCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control
#define SYSCTL_RCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control
#define SYSCTL_RCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed
#define SYSCTL_RCGC0_ADCSPD125K 0x00000000 // 125K samples/second
#define SYSCTL_RCGC0_ADCSPD250K 0x00000100 // 250K samples/second
#define SYSCTL_RCGC0_ADCSPD500K 0x00000200 // 500K samples/second
#define SYSCTL_RCGC0_ADCSPD1M 0x00000300 // 1M samples/second
#define SYSCTL_RCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed
#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second
#define SYSCTL_RCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed
#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second
#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control
#define SYSCTL_RCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_RCGC1 register.
//
//*****************************************************************************
#define SYSCTL_RCGC1_EPI0 0x40000000 // EPI0 Clock Gating
#define SYSCTL_RCGC1_I2S0 0x10000000 // I2S0 Clock Gating Control
#define SYSCTL_RCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating
#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating
#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating
#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control
#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control
#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control
#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control
#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control
#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control
#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control
#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control
#define SYSCTL_RCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control
#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control
#define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control
#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control
#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_RCGC2 register.
//
//*****************************************************************************
#define SYSCTL_RCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control
#define SYSCTL_RCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control
#define SYSCTL_RCGC2_USB0 0x00010000 // USB0 Clock Gating Control
#define SYSCTL_RCGC2_UDMA 0x00002000 // UDMA Clock Gating Control
#define SYSCTL_RCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control
#define SYSCTL_RCGC2_GPIOH 0x00000080 // Port H Clock Gating Control
#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control
#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control
#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control
#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control
#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control
#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control
#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_SCGC0 register.
//
//*****************************************************************************
#define SYSCTL_SCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control
#define SYSCTL_SCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control
#define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control
#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control
#define SYSCTL_SCGC0_PWM 0x00100000 // PWM Clock Gating Control
#define SYSCTL_SCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control
#define SYSCTL_SCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control
#define SYSCTL_SCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed
#define SYSCTL_SCGC0_ADCSPD125K 0x00000000 // 125K samples/second
#define SYSCTL_SCGC0_ADCSPD250K 0x00000100 // 250K samples/second
#define SYSCTL_SCGC0_ADCSPD500K 0x00000200 // 500K samples/second
#define SYSCTL_SCGC0_ADCSPD1M 0x00000300 // 1M samples/second
#define SYSCTL_SCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed
#define SYSCTL_SCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second
#define SYSCTL_SCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed
#define SYSCTL_SCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second
#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control
#define SYSCTL_SCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_SCGC1 register.
//
//*****************************************************************************
#define SYSCTL_SCGC1_EPI0 0x40000000 // EPI0 Clock Gating
#define SYSCTL_SCGC1_I2S0 0x10000000 // I2S 0 Clock Gating
#define SYSCTL_SCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating
#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating
#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating
#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control
#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control
#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control
#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control
#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control
#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control
#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control
#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control
#define SYSCTL_SCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control
#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control
#define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control
#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control
#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_SCGC2 register.
//
//*****************************************************************************
#define SYSCTL_SCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control
#define SYSCTL_SCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control
#define SYSCTL_SCGC2_USB0 0x00010000 // USB0 Clock Gating Control
#define SYSCTL_SCGC2_UDMA 0x00002000 // UDMA Clock Gating Control
#define SYSCTL_SCGC2_GPIOJ 0x00000100 // GPIO Port J Present
#define SYSCTL_SCGC2_GPIOH 0x00000080 // Port H Clock Gating Control
#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control
#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control
#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control
#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control
#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control
#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Contr⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -