📄 hw_adc.h
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//*****************************************************************************
#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select
#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable
#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence
#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Diff Input Select
#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select
#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable
#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence
#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Diff Input Select
#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select
#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable
#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence
#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Diff Input Select
#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select
#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable
#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence
#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Diff Input Select
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
//
//*****************************************************************************
#define ADC_SSFIFO1_DATA_M 0x000003FF // Conversion Result Data
#define ADC_SSFIFO1_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
//
//*****************************************************************************
#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full
#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty
#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer
#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer
#define ADC_SSFSTAT1_HPTR_S 4
#define ADC_SSFSTAT1_TPTR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSOP1 register.
//
//*****************************************************************************
#define ADC_SSOP1_S3DCOP 0x00001000 // Sample 3 Digital Comparator
// Operation
#define ADC_SSOP1_S2DCOP 0x00000100 // Sample 2 Digital Comparator
// Operation
#define ADC_SSOP1_S1DCOP 0x00000010 // Sample 1 Digital Comparator
// Operation
#define ADC_SSOP1_S0DCOP 0x00000001 // Sample 0 Digital Comparator
// Operation
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSDC1 register.
//
//*****************************************************************************
#define ADC_SSDC1_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
// Select
#define ADC_SSDC1_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
// Select
#define ADC_SSDC1_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
// Select
#define ADC_SSDC1_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
// Select
#define ADC_SSDC1_S2DCSEL_S 8
#define ADC_SSDC1_S1DCSEL_S 4
#define ADC_SSDC1_S0DCSEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSMUX2 register.
//
//*****************************************************************************
#define ADC_SSMUX2_MUX3_M 0x0000F000 // 4th Sample Input Select
#define ADC_SSMUX2_MUX2_M 0x00000F00 // 3rd Sample Input Select
#define ADC_SSMUX2_MUX1_M 0x000000F0 // 2nd Sample Input Select
#define ADC_SSMUX2_MUX0_M 0x0000000F // 1st Sample Input Select
#define ADC_SSMUX2_MUX3_S 12
#define ADC_SSMUX2_MUX2_S 8
#define ADC_SSMUX2_MUX1_S 4
#define ADC_SSMUX2_MUX0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSCTL2 register.
//
//*****************************************************************************
#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select
#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable
#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence
#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Diff Input Select
#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select
#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable
#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence
#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Diff Input Select
#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select
#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable
#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence
#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Diff Input Select
#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select
#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable
#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence
#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Diff Input Select
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
//
//*****************************************************************************
#define ADC_SSFIFO2_DATA_M 0x000003FF // Conversion Result Data
#define ADC_SSFIFO2_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
//
//*****************************************************************************
#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full
#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty
#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer
#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer
#define ADC_SSFSTAT2_HPTR_S 4
#define ADC_SSFSTAT2_TPTR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSOP2 register.
//
//*****************************************************************************
#define ADC_SSOP2_S3DCOP 0x00001000 // Sample 3 Digital Comparator
// Operation
#define ADC_SSOP2_S2DCOP 0x00000100 // Sample 2 Digital Comparator
// Operation
#define ADC_SSOP2_S1DCOP 0x00000010 // Sample 1 Digital Comparator
// Operation
#define ADC_SSOP2_S0DCOP 0x00000001 // Sample 0 Digital Comparator
// Operation
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSDC2 register.
//
//*****************************************************************************
#define ADC_SSDC2_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
// Select
#define ADC_SSDC2_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
// Select
#define ADC_SSDC2_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
// Select
#define ADC_SSDC2_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
// Select
#define ADC_SSDC2_S2DCSEL_S 8
#define ADC_SSDC2_S1DCSEL_S 4
#define ADC_SSDC2_S0DCSEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSMUX3 register.
//
//*****************************************************************************
#define ADC_SSMUX3_MUX0_M 0x0000000F // 1st Sample Input Select
#define ADC_SSMUX3_MUX0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSCTL3 register.
//
//*****************************************************************************
#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select
#define ADC_SSCTL3_IE0 0x00000004 // 1st Sample Interrupt Enable
#define ADC_SSCTL3_END0 0x00000002 // 1st Sample is End of Sequence
#define ADC_SSCTL3_D0 0x00000001 // 1st Sample Diff Input Select
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
//
//*****************************************************************************
#define ADC_SSFIFO3_DATA_M 0x000003FF // Conversion Result Data
#define ADC_SSFIFO3_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
//
//*****************************************************************************
#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full
#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty
#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer
#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer
#define ADC_SSFSTAT3_HPTR_S 4
#define ADC_SSFSTAT3_TPTR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSOP3 register.
//
//*****************************************************************************
#define ADC_SSOP3_S0DCOP 0x00000001 // Sample 0 Digital Comparator
// Operation
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSDC3 register.
//
//*****************************************************************************
#define ADC_SSDC3_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
// Select
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_TMLB register.
//
//*****************************************************************************
#define ADC_TMLB_LB 0x00000001 // Loopback control signals
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_DCRIC register.
//
//*****************************************************************************
#define ADC_DCRIC_DCTRIG7 0x00800000 // Digital Comparator Trigger 7
#define ADC_DCRIC_DCTRIG6 0x00400000 // Digital Comparator Trigger 6
#define ADC_DCRIC_DCTRIG5 0x00200000 // Digital Comparator Trigger 5
#define ADC_DCRIC_DCTRIG4 0x00100000 // Digital Comparator Trigger 4
#define ADC_DCRIC_DCTRIG3 0x00080000 // Digital Comparator Trigger 3
#define ADC_DCRIC_DCTRIG2 0x00040000 // Digital Comparator Trigger 2
#define ADC_DCRIC_DCTRIG1 0x00020000 // Digital Comparator Trigger 1
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