hw_adc.h

基于TI公司Cortex-M3的uart超级通信开发

//*****************************************************************************
//
// hw_adc.h - Macros used when accessing the ADC hardware.
//
// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
// Software License Agreement
// 
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
// 
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws.  All rights are reserved.  You may not combine
// this software with "viral" open-source software in order to form a larger
// program.  Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
// 
// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
// 
// This is part of revision 5228 of the Stellaris Firmware Development Package.
//
//*****************************************************************************

#ifndef __HW_ADC_H__
#define __HW_ADC_H__

//*****************************************************************************
//
// The following are defines for the ADC register offsets.
//
//*****************************************************************************
#define ADC_O_ACTSS             0x00000000  // Active sample register
#define ADC_O_RIS               0x00000004  // Raw interrupt status register
#define ADC_O_IM                0x00000008  // Interrupt mask register
#define ADC_O_ISC               0x0000000C  // Interrupt status/clear register
#define ADC_O_OSTAT             0x00000010  // Overflow status register
#define ADC_O_EMUX              0x00000014  // Event multiplexer select reg
#define ADC_O_USTAT             0x00000018  // Underflow status register
#define ADC_O_SSPRI             0x00000020  // Channel priority register
#define ADC_O_PSSI              0x00000028  // Processor sample initiate reg
#define ADC_O_SAC               0x00000030  // Sample Averaging Control reg
#define ADC_O_DCISC             0x00000034  // ADC Digital Comparator Interrupt
                                            // Status and Clear
#define ADC_O_CTL               0x00000038  // ADC Control
#define ADC_O_SSMUX0            0x00000040  // Multiplexer select 0 register
#define ADC_O_SSCTL0            0x00000044  // Sample sequence control 0 reg
#define ADC_O_SSFIFO0           0x00000048  // Result FIFO 0 register
#define ADC_O_SSFSTAT0          0x0000004C  // FIFO 0 status register
#define ADC_O_SSOP0             0x00000050  // ADC Sample Sequence 0 Operation
#define ADC_O_SSDC0             0x00000054  // ADC Sample Sequence 0 Digital
                                            // Comparator Select
#define ADC_O_SSMUX1            0x00000060  // Multiplexer select 1 register
#define ADC_O_SSCTL1            0x00000064  // Sample sequence control 1 reg
#define ADC_O_SSFIFO1           0x00000068  // Result FIFO 1 register
#define ADC_O_SSFSTAT1          0x0000006C  // FIFO 1 status register
#define ADC_O_SSOP1             0x00000070  // ADC Sample Sequence 1 Operation
#define ADC_O_SSDC1             0x00000074  // ADC Sample Sequence 1 Digital
                                            // Comparator Select
#define ADC_O_SSMUX2            0x00000080  // Multiplexer select 2 register
#define ADC_O_SSCTL2            0x00000084  // Sample sequence control 2 reg
#define ADC_O_SSFIFO2           0x00000088  // Result FIFO 2 register
#define ADC_O_SSFSTAT2          0x0000008C  // FIFO 2 status register
#define ADC_O_SSOP2             0x00000090  // ADC Sample Sequence 2 Operation
#define ADC_O_SSDC2             0x00000094  // ADC Sample Sequence 2 Digital
                                            // Comparator Select
#define ADC_O_SSMUX3            0x000000A0  // Multiplexer select 3 register
#define ADC_O_SSCTL3            0x000000A4  // Sample sequence control 3 reg
#define ADC_O_SSFIFO3           0x000000A8  // Result FIFO 3 register
#define ADC_O_SSFSTAT3          0x000000AC  // FIFO 3 status register
#define ADC_O_SSOP3             0x000000B0  // ADC Sample Sequence 3 Operation
#define ADC_O_SSDC3             0x000000B4  // ADC Sample Sequence 3 Digital
                                            // Comparator Select
#define ADC_O_TMLB              0x00000100  // Test mode loopback register
#define ADC_O_DCRIC             0x00000D00  // ADC Digital Comparator Reset
                                            // Initial Conditions
#define ADC_O_DCCTL0            0x00000E00  // ADC Digital Comparator Control 0
#define ADC_O_DCCTL1            0x00000E04  // ADC Digital Comparator Control 1
#define ADC_O_DCCTL2            0x00000E08  // ADC Digital Comparator Control 2
#define ADC_O_DCCTL3            0x00000E0C  // ADC Digital Comparator Control 3
#define ADC_O_DCCTL4            0x00000E10  // ADC Digital Comparator Control 4
#define ADC_O_DCCTL5            0x00000E14  // ADC Digital Comparator Control 5
#define ADC_O_DCCTL6            0x00000E18  // ADC Digital Comparator Control 6
#define ADC_O_DCCTL7            0x00000E1C  // ADC Digital Comparator Control 7
#define ADC_O_DCCMP0            0x00000E40  // ADC Digital Comparator Range 0
#define ADC_O_DCCMP1            0x00000E44  // ADC Digital Comparator Range 1
#define ADC_O_DCCMP2            0x00000E48  // ADC Digital Comparator Range 2
#define ADC_O_DCCMP3            0x00000E4C  // ADC Digital Comparator Range 3
#define ADC_O_DCCMP4            0x00000E50  // ADC Digital Comparator Range 4
#define ADC_O_DCCMP5            0x00000E54  // ADC Digital Comparator Range 5
#define ADC_O_DCCMP6            0x00000E58  // ADC Digital Comparator Range 6
#define ADC_O_DCCMP7            0x00000E5C  // ADC Digital Comparator Range 7

//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_ACTSS register.
//
//*****************************************************************************
#define ADC_ACTSS_ASEN3         0x00000008  // Sample sequence 3 enable
#define ADC_ACTSS_ASEN2         0x00000004  // Sample sequence 2 enable
#define ADC_ACTSS_ASEN1         0x00000002  // Sample sequence 1 enable
#define ADC_ACTSS_ASEN0         0x00000001  // Sample sequence 0 enable

//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_RIS register.
//
//*****************************************************************************
#define ADC_RIS_INRDC           0x00010000  // Digital Comparator Raw Interrupt
                                            // Status
#define ADC_RIS_INR3            0x00000008  // Sample sequence 3 interrupt
#define ADC_RIS_INR2            0x00000004  // Sample sequence 2 interrupt
#define ADC_RIS_INR1            0x00000002  // Sample sequence 1 interrupt
#define ADC_RIS_INR0            0x00000001  // Sample sequence 0 interrupt

//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_IM register.
//
//*****************************************************************************
#define ADC_IM_DCONSS3          0x00080000  // Digital Comparator Interrupt on
                                            // SS3
#define ADC_IM_DCONSS2          0x00040000  // Digital Comparator Interrupt on
                                            // SS2
#define ADC_IM_DCONSS1          0x00020000  // Digital Comparator Interrupt on
                                            // SS1
#define ADC_IM_DCONSS0          0x00010000  // Digital Comparator Interrupt on
                                            // SS0
#define ADC_IM_MASK3            0x00000008  // Sample sequence 3 mask
#define ADC_IM_MASK2            0x00000004  // Sample sequence 2 mask
#define ADC_IM_MASK1            0x00000002  // Sample sequence 1 mask
#define ADC_IM_MASK0            0x00000001  // Sample sequence 0 mask

//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_ISC register.
//
//*****************************************************************************
#define ADC_ISC_DCINSS3         0x00080000  // Digital Comparator Interrupt
                                            // Status on SS3
#define ADC_ISC_DCINSS2         0x00040000  // Digital Comparator Interrupt
                                            // Status on SS2
#define ADC_ISC_DCINSS1         0x00020000  // Digital Comparator Interrupt
                                            // Status on SS1
#define ADC_ISC_DCINSS0         0x00010000  // Digital Comparator Interrupt
                                            // Status on SS0
#define ADC_ISC_IN3             0x00000008  // Sample sequence 3 interrupt
#define ADC_ISC_IN2             0x00000004  // Sample sequence 2 interrupt
#define ADC_ISC_IN1             0x00000002  // Sample sequence 1 interrupt
#define ADC_ISC_IN0             0x00000001  // Sample sequence 0 interrupt

//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_OSTAT register.
//
//*****************************************************************************
#define ADC_OSTAT_OV3           0x00000008  // Sample sequence 3 overflow
#define ADC_OSTAT_OV2           0x00000004  // Sample sequence 2 overflow
#define ADC_OSTAT_OV1           0x00000002  // Sample sequence 1 overflow
#define ADC_OSTAT_OV0           0x00000001  // Sample sequence 0 overflow

//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_EMUX register.
//
//*****************************************************************************
#define ADC_EMUX_EM3_M          0x0000F000  // Event mux 3 mask
#define ADC_EMUX_EM3_PROCESSOR  0x00000000  // Processor event
#define ADC_EMUX_EM3_COMP0      0x00001000  // Analog comparator 0 event
#define ADC_EMUX_EM3_COMP1      0x00002000  // Analog comparator 1 event
#define ADC_EMUX_EM3_COMP2      0x00003000  // Analog comparator 2 event
#define ADC_EMUX_EM3_EXTERNAL   0x00004000  // External event
#define ADC_EMUX_EM3_TIMER      0x00005000  // Timer event
#define ADC_EMUX_EM3_PWM0       0x00006000  // PWM0 event
#define ADC_EMUX_EM3_PWM1       0x00007000  // PWM1 event
#define ADC_EMUX_EM3_PWM2       0x00008000  // PWM2 event
#define ADC_EMUX_EM3_PWM3       0x00009000  // PWM3
#define ADC_EMUX_EM3_ALWAYS     0x0000F000  // Always event
#define ADC_EMUX_EM2_M          0x00000F00  // Event mux 2 mask
#define ADC_EMUX_EM2_PROCESSOR  0x00000000  // Processor event
#define ADC_EMUX_EM2_COMP0      0x00000100  // Analog comparator 0 event
#define ADC_EMUX_EM2_COMP1      0x00000200  // Analog comparator 1 event
#define ADC_EMUX_EM2_COMP2      0x00000300  // Analog comparator 2 event
#define ADC_EMUX_EM2_EXTERNAL   0x00000400  // External event
#define ADC_EMUX_EM2_TIMER      0x00000500  // Timer event
#define ADC_EMUX_EM2_PWM0       0x00000600  // PWM0 event
#define ADC_EMUX_EM2_PWM1       0x00000700  // PWM1 event
#define ADC_EMUX_EM2_PWM2       0x00000800  // PWM2 event
#define ADC_EMUX_EM2_PWM3       0x00000900  // PWM3
#define ADC_EMUX_EM2_ALWAYS     0x00000F00  // Always event
#define ADC_EMUX_EM1_M          0x000000F0  // Event mux 1 mask
#define ADC_EMUX_EM1_PROCESSOR  0x00000000  // Processor event
#define ADC_EMUX_EM1_COMP0      0x00000010  // Analog comparator 0 event
#define ADC_EMUX_EM1_COMP1      0x00000020  // Analog comparator 1 event
#define ADC_EMUX_EM1_COMP2      0x00000030  // Analog comparator 2 event
#define ADC_EMUX_EM1_EXTERNAL   0x00000040  // External event
#define ADC_EMUX_EM1_TIMER      0x00000050  // Timer event
#define ADC_EMUX_EM1_PWM0       0x00000060  // PWM0 event
#define ADC_EMUX_EM1_PWM1       0x00000070  // PWM1 event
#define ADC_EMUX_EM1_PWM2       0x00000080  // PWM2 event
#define ADC_EMUX_EM1_PWM3       0x00000090  // PWM3
#define ADC_EMUX_EM1_ALWAYS     0x000000F0  // Always event
#define ADC_EMUX_EM0_M          0x0000000F  // Event mux 0 mask
#define ADC_EMUX_EM0_PROCESSOR  0x00000000  // Processor event
#define ADC_EMUX_EM0_COMP0      0x00000001  // Analog comparator 0 event
#define ADC_EMUX_EM0_COMP1      0x00000002  // Analog comparator 1 event
#define ADC_EMUX_EM0_COMP2      0x00000003  // Analog comparator 2 event
#define ADC_EMUX_EM0_EXTERNAL   0x00000004  // External event
#define ADC_EMUX_EM0_TIMER      0x00000005  // Timer event
#define ADC_EMUX_EM0_PWM0       0x00000006  // PWM0 event
#define ADC_EMUX_EM0_PWM1       0x00000007  // PWM1 event
#define ADC_EMUX_EM0_PWM2       0x00000008  // PWM2 event
#define ADC_EMUX_EM0_PWM3       0x00000009  // PWM3
#define ADC_EMUX_EM0_ALWAYS     0x0000000F  // Always event

//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_USTAT register.
//
//*****************************************************************************
#define ADC_USTAT_UV3           0x00000008  // Sample sequence 3 underflow
#define ADC_USTAT_UV2           0x00000004  // Sample sequence 2 underflow
#define ADC_USTAT_UV1           0x00000002  // Sample sequence 1 underflow
#define ADC_USTAT_UV0           0x00000001  // Sample sequence 0 underflow

//*****************************************************************************