📄 hw_ethernet.h
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// Activity
#define MAC_LED_LED0_M 0x0000000F // LED0 Source
#define MAC_LED_LED0_LINK 0x00000000 // Link OK (Default LED0)
#define MAC_LED_LED0_RXTX 0x00000001 // RX or TX Activity
#define MAC_LED_LED0_100 0x00000005 // 100BASE-TX mode
#define MAC_LED_LED0_10 0x00000006 // 10BASE-T mode
#define MAC_LED_LED0_DUPLEX 0x00000007 // Full-Duplex
#define MAC_LED_LED0_LINKACT 0x00000008 // Link OK & Blink=RX or TX
// Activity
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_O_MDIX register.
//
//*****************************************************************************
#define MAC_MDIX_EN 0x00000001 // MDI/MDI-X Enable
//*****************************************************************************
//
// The following are defines for the Ethernet Controller PHY registers.
//
//*****************************************************************************
#define PHY_MR0 0x00000000 // Ethernet PHY Management Register
// 0 - Control
#define PHY_MR1 0x00000001 // Ethernet PHY Management Register
// 1 - Status
#define PHY_MR2 0x00000002 // Ethernet PHY Management Register
// 2 - PHY Identifier 1
#define PHY_MR3 0x00000003 // Ethernet PHY Management Register
// 3 - PHY Identifier 2
#define PHY_MR4 0x00000004 // Ethernet PHY Management Register
// 4 - Auto-Negotiation
// Advertisement
#define PHY_MR5 0x00000005 // Ethernet PHY Management Register
// 5 - Auto-Negotiation Link
// Partner Base Page Ability
#define PHY_MR6 0x00000006 // Ethernet PHY Management Register
// 6 - Auto-Negotiation Expansion
#define PHY_MR16 0x00000010 // Ethernet PHY Management Register
// 16 - Vendor-Specific
#define PHY_MR17 0x00000011 // Ethernet PHY Management Register
// 17 - Interrupt Control/Status
#define PHY_MR18 0x00000012 // Ethernet PHY Management Register
// 18 - Diagnostic
#define PHY_MR19 0x00000013 // Ethernet PHY Management Register
// 19 - Transceiver Control
#define PHY_MR23 0x00000017 // Ethernet PHY Management Register
// 23 - LED Configuration
#define PHY_MR24 0x00000018 // Ethernet PHY Management Register
// 24 -MDI/MDIX Control
#define PHY_MR27 0x0000001B // Ethernet PHY Management Register
// 27 -Special Control/Status
#define PHY_MR29 0x0000001D // Ethernet PHY Management Register
// 29 - Interrupt Status
#define PHY_MR30 0x0000001E // Ethernet PHY Management Register
// 30 - Interrupt Mask
#define PHY_MR31 0x0000001F // Ethernet PHY Management Register
// 31 - PHY Special Control/Status
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR0 register.
//
//*****************************************************************************
#define PHY_MR0_RESET 0x00008000 // Reset Registers
#define PHY_MR0_LOOPBK 0x00004000 // Loopback Mode
#define PHY_MR0_SPEEDSL 0x00002000 // Speed Select
#define PHY_MR0_ANEGEN 0x00001000 // Auto-Negotiation Enable
#define PHY_MR0_PWRDN 0x00000800 // Power Down
#define PHY_MR0_ISO 0x00000400 // Isolate
#define PHY_MR0_RANEG 0x00000200 // Restart Auto-Negotiation
#define PHY_MR0_DUPLEX 0x00000100 // Set Duplex Mode
#define PHY_MR0_COLT 0x00000080 // Collision Test
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR1 register.
//
//*****************************************************************************
#define PHY_MR1_100X_F 0x00004000 // 100BASE-TX Full-Duplex Mode
#define PHY_MR1_100X_H 0x00002000 // 100BASE-TX Half-Duplex Mode
#define PHY_MR1_10T_F 0x00001000 // 10BASE-T Full-Duplex Mode
#define PHY_MR1_10T_H 0x00000800 // 10BASE-T Half-Duplex Mode
#define PHY_MR1_MFPS 0x00000040 // Management Frames with Preamble
// Suppressed
#define PHY_MR1_ANEGC 0x00000020 // Auto-Negotiation Complete
#define PHY_MR1_RFAULT 0x00000010 // Remote Fault
#define PHY_MR1_ANEGA 0x00000008 // Auto-Negotiation
#define PHY_MR1_LINK 0x00000004 // Link Made
#define PHY_MR1_JAB 0x00000002 // Jabber Condition
#define PHY_MR1_EXTD 0x00000001 // Extended Capabilities
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR2 register.
//
//*****************************************************************************
#define PHY_MR2_OUI_M 0x0000FFFF // Organizationally Unique
// Identifier[21:6]
#define PHY_MR2_OUI_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR3 register.
//
//*****************************************************************************
#define PHY_MR3_OUI_M 0x0000FC00 // Organizationally Unique
// Identifier[5:0]
#define PHY_MR3_MN_M 0x000003F0 // Model Number
#define PHY_MR3_RN_M 0x0000000F // Revision Number
#define PHY_MR3_OUI_S 10
#define PHY_MR3_MN_S 4
#define PHY_MR3_RN_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR4 register.
//
//*****************************************************************************
#define PHY_MR4_NP 0x00008000 // Next Page
#define PHY_MR4_RF 0x00002000 // Remote Fault
#define PHY_MR4_A3 0x00000100 // Technology Ability Field[3]
#define PHY_MR4_A2 0x00000080 // Technology Ability Field[2]
#define PHY_MR4_A1 0x00000040 // Technology Ability Field[1]
#define PHY_MR4_A0 0x00000020 // Technology Ability Field[0]
#define PHY_MR4_S_M 0x0000001F // Selector Field
#define PHY_MR4_S_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR5 register.
//
//*****************************************************************************
#define PHY_MR5_NP 0x00008000 // Next Page
#define PHY_MR5_ACK 0x00004000 // Acknowledge
#define PHY_MR5_RF 0x00002000 // Remote Fault
#define PHY_MR5_A_M 0x00001FE0 // Technology Ability Field
#define PHY_MR5_S_M 0x0000001F // Selector Field
#define PHY_MR5_S_8023 0x00000001 // IEEE Std 802.3
#define PHY_MR5_S_8029 0x00000002 // IEEE Std 802.9 ISLAN-16T
#define PHY_MR5_S_8025 0x00000003 // IEEE Std 802.5
#define PHY_MR5_S_1394 0x00000004 // IEEE Std 1394
#define PHY_MR5_A_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR6 register.
//
//*****************************************************************************
#define PHY_MR6_PDF 0x00000010 // Parallel Detection Fault
#define PHY_MR6_LPNPA 0x00000008 // Link Partner is Next Page Able
#define PHY_MR6_PRX 0x00000002 // New Page Received
#define PHY_MR6_LPANEGA 0x00000001 // Link Partner is Auto-Negotiation
// Able
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR16 register.
//
//*****************************************************************************
#define PHY_MR16_RPTR 0x00008000 // Repeater Mode
#define PHY_MR16_INPOL 0x00004000 // Interrupt Polarity
#define PHY_MR16_TXHIM 0x00001000 // Transmit High Impedance Mode
#define PHY_MR16_SQEI 0x00000800 // SQE Inhibit Testing
#define PHY_MR16_NL10 0x00000400 // Natural Loopback Mode
#define PHY_MR16_SR_M 0x000003C0 // Silicon Revision Identifier
#define PHY_MR16_APOL 0x00000020 // Auto-Polarity Disable
#define PHY_MR16_RVSPOL 0x00000010 // Receive Data Polarity
#define PHY_MR16_PCSBP 0x00000002 // PCS Bypass
#define PHY_MR16_RXCC 0x00000001 // Receive Clock Control
#define PHY_MR16_SR_S 6
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR17 register.
//
//*****************************************************************************
#define PHY_MR17_JABBER_IE 0x00008000 // Jabber Interrupt Enable
#define PHY_MR17_FASTRIP 0x00004000 // 10-BASE-T Fast Mode Enable
#define PHY_MR17_RXER_IE 0x00004000 // Receive Error Interrupt Enable
#define PHY_MR17_EDPD 0x00002000 // Enable Energy Detect Power Down
#define PHY_MR17_PRX_IE 0x00002000 // Page Received Interrupt Enable
#define PHY_MR17_PDF_IE 0x00001000 // Parallel Detection Fault
// Interrupt Enable
#define PHY_MR17_LSQE 0x00000800 // Low Squelch Enable
#define PHY_MR17_LPACK_IE 0x00000800 // LP Acknowledge Interrupt Enable
#define PHY_MR17_LSCHG_IE 0x00000400 // Link Status Change Interrupt
// Enable
#define PHY_MR17_RFAULT_IE 0x00000200 // Remote Fault Interrupt Enable
#define PHY_MR17_ANEGCOMP_IE 0x00000100 // Auto-Negotiation Complete
// Interrupt Enable
#define PHY_MR17_FASTEST 0x00000100 // Auto-Negotiation Test Mode
#define PHY_MR17_JABBER_INT 0x00000080 // Jabber Event Interrupt
#define PHY_MR17_RXER_INT 0x00000040 // Receive Error Interrupt
#define PHY_MR17_PRX_INT 0x00000020 // Page Receive Interrupt
#define PHY_MR17_PDF_INT 0x00000010 // Parallel Detection Fault
// Interrupt
#define PHY_MR17_LPACK_INT 0x00000008 // LP Acknowledge Interrupt
#define PHY_MR17_LSCHG_INT 0x00000004 // Link Status Change Interrupt
#define PHY_MR17_FGLS 0x00000004 // Force Good Link Status
#define PHY_MR17_RFAULT_INT 0x00000002 // Remote Fault Interrupt
#define PHY_MR17_ENON 0x00000002 // Energy On
#define PHY_MR17_ANEGCOMP_INT 0x00000001 // Auto-Negotiation Complete
// Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR18 register.
//
//*****************************************************************************
#define PHY_MR18_ANEGF 0x00001000 // Auto-Negotiation Failure
#define PHY_MR18_DPLX 0x00000800 // Duplex Mode
#define PHY_MR18_RATE 0x00000400 // Rate
#define PHY_MR18_RXSD 0x00000200 // Receive Detection
#define PHY_MR18_RX_LOCK 0x00000100 // Receive PLL Lock
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR19 register.
//
//*****************************************************************************
#define PHY_MR19_TXO_M 0x0000C000 // Transmit Amplitude Selection
#define PHY_MR19_TXO_00DB 0x00000000 // Gain set for 0.0dB of insertion
// loss
#define PHY_MR19_TXO_04DB 0x00004000 // Gain set for 0.4dB of insertion
// loss
#define PHY_MR19_TXO_08DB 0x00008000 // Gain set for 0.8dB of insertion
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