set_pinout.c

基于TI公司Cortex-M3的uart超级通信开发

//! appropriately.  In this case, if no EEPROM is found, the EPI configuration
//! will default to that required to use the SDRAM daughter board which is
//! included with the base development kit.
//!
//! If SIMPLE_PINOUT_SET is defined, however, all the dynamic configuration code
//! is replaced with a very simple function which merely sets the pinout and EPI
//! configuration statically.  This is a better representation of how a real-
//! world application would likely initialize the pinout and EPI timing and
//! takes significantly less code space than the dynamic, daughter-board
//! detecting version.  The example offered here sets the pinout and EPI
//! configuration appropriately for the Flash/SRAM/LCD daughter board.

//! \return None.
//
//*****************************************************************************
void
PinoutSet(void)
{
    tDaughterIDInfo sInfo;

    //
    // Enable all GPIO banks.
    //
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ);

    //
    // Determine which daughter board (if any) is currently attached to the
    // development board.
    //
    g_eDaughterType = DaughterBoardTypeGet(&sInfo);

    //
    // Determine the port control settings required to enable the EPI pins
    // and other peripheral signals for this daughter board and set all the
    // GPIO port control registers.
    //
    PortControlSet(&sInfo);

    //
    // Set the pin configuration for the Extended Peripheral Interface (EPI)
    //
    EPIPinConfigSet(&sInfo);
}
#else
//*****************************************************************************
//
// The following simple implementation merely sets the pinout and EPI
// configuration based on a hardcoded set of parameters.  This is less
// flexible but more likely to be the code that is used in a real world
// application where you don't have to worry about supporting multiple
// different daughter boards connected to the EPI.
//
//*****************************************************************************

//*****************************************************************************
//
// Use the following to specify the GPIO pins used by the EPI bus when
// configured in HostBus8 mode.  These basic definitions set up the pins
// required for the Flash/SRAM/LCD daughter board.
//
//*****************************************************************************
#define EPI_PORTA_PINS          0x00
#define EPI_PORTB_PINS          0x30
#define EPI_PORTC_PINS          0xf0
#define EPI_PORTD_PINS          0x0C
#define EPI_PORTE_PINS          0x0F
#define EPI_PORTF_PINS          0x30
#define EPI_PORTG_PINS          0x83
#define EPI_PORTH_PINS          0xFF
#define EPI_PORTJ_PINS          0x7f

//*****************************************************************************
//
// Deviations from the standard EPI pin configuration required for use with
// the SRAM/Flash daughter board which uses EPI HostBus8 mode and repurposes
// some of the LCD control signal GPIOs for this.
//
//*****************************************************************************

//*****************************************************************************
//
// Configures all pins associated with the Extended Peripheral Interface (EPI).
//
// \param eDaughter identifies the attached daughter board (if any).
//
// This function configures all pins forming part of the EPI on the device and
// configures the EPI peripheral appropriately for whichever hardware we
// detect is connected to it. On exit, the EPI peripheral is enabled and all
// pins associated with the interface are configured as EPI signals. Drive
// strength is set to 8mA for all pins.
//
//*****************************************************************************
static void
EPIPinConfigSet(void)
{
    //
    // Enable the EPI peripheral
    //
    SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);

    //
    // Configure the EPI pins that are to be used on this board.
    //
#if (EPI_PORTA_PINS != 0x00)
    GPIOPadConfigSet(GPIO_PORTA_BASE, EPI_PORTA_PINS, GPIO_STRENGTH_8MA,
                     GPIO_PIN_TYPE_STD_WPU);
    GPIODirModeSet(GPIO_PORTA_BASE, EPI_PORTA_PINS, GPIO_DIR_MODE_HW);
#endif
#if (EPI_PORTC_PINS != 0x00)
    GPIOPadConfigSet(GPIO_PORTC_BASE, EPI_PORTC_PINS, GPIO_STRENGTH_8MA,
                     GPIO_PIN_TYPE_STD_WPU);
    GPIODirModeSet(GPIO_PORTC_BASE, EPI_PORTC_PINS, GPIO_DIR_MODE_HW);
#endif
#if EPI_PORTE_PINS
    GPIOPadConfigSet(GPIO_PORTE_BASE, EPI_PORTE_PINS, GPIO_STRENGTH_8MA,
                     GPIO_PIN_TYPE_STD_WPU);
    GPIODirModeSet(GPIO_PORTE_BASE, EPI_PORTE_PINS, GPIO_DIR_MODE_HW);
#endif
#if EPI_PORTF_PINS
    GPIOPadConfigSet(GPIO_PORTF_BASE, EPI_PORTF_PINS, GPIO_STRENGTH_8MA,
                     GPIO_PIN_TYPE_STD_WPU);
    GPIODirModeSet(GPIO_PORTF_BASE, EPI_PORTF_PINS, GPIO_DIR_MODE_HW);
#endif
#if EPI_PORTG_PINS
    GPIOPadConfigSet(GPIO_PORTG_BASE, EPI_PORTG_PINS, GPIO_STRENGTH_8MA,
                     GPIO_PIN_TYPE_STD_WPU);
    GPIODirModeSet(GPIO_PORTG_BASE, EPI_PORTG_PINS, GPIO_DIR_MODE_HW);
#endif
#if EPI_PORTJ_PINS
    GPIOPadConfigSet(GPIO_PORTJ_BASE, EPI_PORTJ_PINS, GPIO_STRENGTH_8MA,
                     GPIO_PIN_TYPE_STD_WPU);
    GPIODirModeSet(GPIO_PORTJ_BASE, EPI_PORTJ_PINS, GPIO_DIR_MODE_HW);
#endif

#if (EPI_PORTB_PINS != 0x00)
    GPIOPadConfigSet(GPIO_PORTB_BASE, EPI_PORTB_PINS, GPIO_STRENGTH_8MA,
                     GPIO_PIN_TYPE_STD_WPU);
    GPIODirModeSet(GPIO_PORTB_BASE, EPI_PORTB_PINS,
                   GPIO_DIR_MODE_HW);
#endif
#if (EPI_PORTD_PINS != 0x00)
    GPIOPadConfigSet(GPIO_PORTD_BASE, EPI_PORTD_PINS, GPIO_STRENGTH_8MA,
                     GPIO_PIN_TYPE_STD_WPU);
    GPIODirModeSet(GPIO_PORTD_BASE, EPI_PORTD_PINS,
                   GPIO_DIR_MODE_HW);
#endif
#if EPI_PORTH_PINS
    GPIOPadConfigSet(GPIO_PORTH_BASE, EPI_PORTH_PINS,GPIO_STRENGTH_8MA,
                     GPIO_PIN_TYPE_STD_WPU);
    GPIODirModeSet(GPIO_PORTH_BASE, EPI_PORTH_PINS,
                   GPIO_DIR_MODE_HW);
#endif

    //
    // Set the EPI operating mode for the Flash/SRAM/LCD daughter board.
    // The values used here set the EPI to run at the system clock rate and
    // will allow the board memories and LCD interface to be timed correctly
    // as long as the system clock is no higher than 50MHz.
    //
    EPIModeSet(EPI0_BASE, EPI_MODE_HB8);
    EPIDividerSet(EPI0_BASE, 0);
    EPIConfigHB8Set(EPI0_BASE, (EPI_HB8_MODE_ADMUX | EPI_HB8_WRWAIT_1 |
                    EPI_HB8_RDWAIT_1 | EPI_HB8_WORD_ACCESS), 0);
    EPIAddressMapSet(EPI0_BASE, (EPI_ADDR_RAM_SIZE_256MB |
                     EPI_ADDR_RAM_BASE_6) );
}

//*****************************************************************************
//
//! Configures the LM3S9B96 device pinout for the development board.
//!
//! This function configures each pin of the lm3s9b96 device to route the
//! appropriate peripheral signal as required by the design of the
//! dk-lm3s9b96 development board.
//!
//! \return None.
//
//*****************************************************************************
void
PinoutSet(void)
{
    //
    // Hardcode the daughter board type to the Flash/SRAM/LCD board since this
    // is the EPI configuration we set when SIMPLE_PINOUT_SET is defined.
    //
    g_eDaughterType = DAUGHTER_SRAM_FLASH;

    //
    // Enable all GPIO banks.
    //
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ);

    //
    // GPIO Port A pins
    //
    // To use CAN0, this register value must be changed. The value here
    // enables USB functionality instead of CAN. For CAN, use....
    //
    //  HWREG(GPIO_PORTA_BASE + GPIO_O_PCTL) = GPIO_PCTL_PA0_U0RX |
    //                                         GPIO_PCTL_PA1_U0TX |
    //                                         GPIO_PCTL_PA2_SSI0CLK |
    //                                         GPIO_PCTL_PA3_SSI0FSS |
    //                                         GPIO_PCTL_PA4_SSI0RX |
    //                                         GPIO_PCTL_PA5_SSI0TX |
    //                                         GPIO_PCTL_PA6_CAN0RX |
    //                                         GPIO_PCTL_PA7_CAN0TX;
    //
    //
    HWREG(GPIO_PORTA_BASE + GPIO_O_PCTL) = GPIO_PCTL_PA0_U0RX |
                                           GPIO_PCTL_PA1_U0TX |
                                           GPIO_PCTL_PA2_SSI0CLK |
                                           GPIO_PCTL_PA3_SSI0FSS |
                                           GPIO_PCTL_PA4_SSI0RX |
                                           GPIO_PCTL_PA5_SSI0TX |
                                           GPIO_PCTL_PA6_USB0EPEN |
                                           GPIO_PCTL_PA7_USB0PFLT;

    //
    // GPIO Port B pins
    //
    HWREG(GPIO_PORTB_BASE + GPIO_O_PCTL) = GPIO_PCTL_PB2_I2C0SCL |
                                           GPIO_PCTL_PB3_I2C0SDA |
                                           GPIO_PCTL_PB4_EPI0S23 |
                                           GPIO_PCTL_PB5_EPI0S22 |
                                           GPIO_PCTL_PB6_I2S0TXSCK |
                                           GPIO_PCTL_PB7_NMI;

    //
    // GPIO Port C pins
    //
    HWREG(GPIO_PORTC_BASE + GPIO_O_PCTL) = GPIO_PCTL_PC0_TCK |
                                           GPIO_PCTL_PC1_TMS |
                                           GPIO_PCTL_PC2_TDI |
                                           GPIO_PCTL_PC3_TDO |
                                           GPIO_PCTL_PC4_EPI0S2 |
                                           GPIO_PCTL_PC5_EPI0S3 |
                                           GPIO_PCTL_PC6_EPI0S4 |
                                           GPIO_PCTL_PC7_EPI0S5;

    //
    // GPIO Port D pins.
    //
    HWREG(GPIO_PORTD_BASE + GPIO_O_PCTL) = GPIO_PCTL_PD0_I2S0RXSCK |
                                           GPIO_PCTL_PD1_I2S0RXWS |
                                           GPIO_PCTL_PD2_EPI0S20 |
                                           GPIO_PCTL_PD3_EPI0S21 |
                                           GPIO_PCTL_PD4_I2S0RXSD |
                                           GPIO_PCTL_PD5_I2S0RXMCLK;

    //
    // GPIO Port E pins
    //
    HWREG(GPIO_PORTE_BASE + GPIO_O_PCTL) = GPIO_PCTL_PE0_EPI0S8 |
                                           GPIO_PCTL_PE1_EPI0S9 |
                                           GPIO_PCTL_PE2_EPI0S24 |
                                           GPIO_PCTL_PE3_EPI0S25 |
                                           GPIO_PCTL_PE4_I2S0TXWS |
                                           GPIO_PCTL_PE5_I2S0TXSD;

    //
    // GPIO Port F pins
    //
    HWREG(GPIO_PORTF_BASE + GPIO_O_PCTL) = GPIO_PCTL_PF1_I2S0TXMCLK |
                                           GPIO_PCTL_PF2_LED1 |
                                           GPIO_PCTL_PF3_LED0 |
                                           GPIO_PCTL_PF4_EPI0S12 |
                                           GPIO_PCTL_PF5_EPI0S15;

    //
    // GPIO Port G pins
    //
    HWREG(GPIO_PORTG_BASE + GPIO_O_PCTL) = GPIO_PCTL_PG0_EPI0S13 |
                                           GPIO_PCTL_PG1_EPI0S14 |
                                           GPIO_PCTL_PG7_EPI0S31;

    //
    // GPIO Port H pins
    //
    HWREG(GPIO_PORTH_BASE + GPIO_O_PCTL) = GPIO_PCTL_PH0_EPI0S6 |
                                           GPIO_PCTL_PH1_EPI0S7 |
                                           GPIO_PCTL_PH2_EPI0S1 |
                                           GPIO_PCTL_PH3_EPI0S0 |
                                           GPIO_PCTL_PH4_EPI0S10 |
                                           GPIO_PCTL_PH5_EPI0S11 |
                                           GPIO_PCTL_PH6_EPI0S26 |
                                           GPIO_PCTL_PH7_EPI0S27;
    //
    // GPIO Port J pins
    //
    HWREG(GPIO_PORTJ_BASE + GPIO_O_PCTL) = GPIO_PCTL_PJ0_EPI0S16 |
                                           GPIO_PCTL_PJ1_EPI0S17 |
                                           GPIO_PCTL_PJ2_EPI0S18 |
                                           GPIO_PCTL_PJ3_EPI0S19 |
                                           GPIO_PCTL_PJ4_EPI0S28 |
                                           GPIO_PCTL_PJ5_EPI0S29 |
                                           GPIO_PCTL_PJ6_EPI0S30;

    //
    // Configure pins and interface for the EPI-connected devices.
    //
    EPIPinConfigSet();
}
#endif

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************