set_pinout.c

基于TI公司Cortex-M3的uart超级通信开发

//*****************************************************************************
//
// set_pinout.c - Functions related to configuration of the device pinout.
//
// Copyright (c) 2009 Luminary Micro, Inc.  All rights reserved.
// Software License Agreement
// 
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
// 
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws.  All rights are reserved.  You may not combine
// this software with "viral" open-source software in order to form a larger
// program.  Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
// 
// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
// 
//
//*****************************************************************************

#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "inc/hw_gpio.h"
#include "driverlib/sysctl.h"
#include "driverlib/i2c.h"
#include "driverlib/gpio.h"
#include "driverlib/epi.h"
#include "driverlib/debug.h"
#include "set_pinout.h"

//*****************************************************************************
//
//! \addtogroup set_pinout_api
//! @{
//
//*****************************************************************************

//*****************************************************************************
//
// NOTE: This module can be built in two ways.  If the label SIMPLE_PINOUT_SET
// is not defined, the PinoutSet() function will attempt to read an I2C EEPROM
// to determine which daughter board is attached to the development kit board
// and use information from that EEPROM to dynamically configure the EPI
// appropriately.  In this case, if no EEPROM is found, the EPI configuration
// will default to that required to use the SDRAM daughter board which is
// included with the base development kit.
//
// If SIMPLE_PINOUT_SET is defined, however, all the dynamic configuration code
// is replaced with a very simple function which merely sets the pinout and EPI
// configuration statically.  This is a better representation of how a real-
// world application would likely initialize the pinout and EPI timing and
// takes significantly less code space than the dynamic, daughter-board
// detecting version.  The example offered here sets the pinout and EPI
// configuration appropriately for the Flash/SRAM/LCD daughter board.
//
//*****************************************************************************

//*****************************************************************************
//
// A global variable indicating which daughter board, if any, is currently
// connected to the lm3s9b96 development board.
//
//*****************************************************************************
tDaughterBoard g_eDaughterType;

#ifndef SIMPLE_PINOUT_SET
//*****************************************************************************
//
// The maximum number of GPIO ports.
//
//*****************************************************************************
#define NUM_GPIO_PORTS  9

//*****************************************************************************
//
// Base addresses of the GPIO ports that may contain EPI signals.  The index
// into this array must correlate with the index in the ucPortIndex field of
// tEPIPinInfo.
//
//*****************************************************************************
const unsigned long g_pulGPIOBase[NUM_GPIO_PORTS] =
{
    GPIO_PORTA_BASE,
    GPIO_PORTB_BASE,
    GPIO_PORTC_BASE,
    GPIO_PORTD_BASE,
    GPIO_PORTE_BASE,
    GPIO_PORTF_BASE,
    GPIO_PORTG_BASE,
    GPIO_PORTH_BASE,
    GPIO_PORTJ_BASE
};

//*****************************************************************************
//
// Structure used to map an EPI signal to a GPIO port and pin on the target
// part (lm3s9b96 in this case).  Field ucPortIndex is the index into the
// g_pulGPIOBase array containing the base address of the port.
//
//*****************************************************************************
typedef struct
{
    unsigned char ucPortIndex;
    unsigned char ucPctl;
    unsigned char ucPin;
}
tEPIPinInfo;

//*****************************************************************************
//
// The maximum number of EPI interface signals (EPI0Sxx).
//
//*****************************************************************************
#define NUM_EPI_SIGNALS 32

//*****************************************************************************
//
// The number of EPI clock periods for a write access with no wait states.
//
//*****************************************************************************
#define EPI_WRITE_CYCLES 4

//*****************************************************************************
//
// The number of EPI clock periods for a read access with no wait states.
//
//*****************************************************************************
#define EPI_READ_CYCLES  4

//*****************************************************************************
//
// The number of EPI clock periods added for each wait state.
//
//*****************************************************************************
#define EPI_WS_CYCLES    2

//*****************************************************************************
//
// This array holds the information necessary to map an EPI signal to a
// particular GPIO port and pin on the target part (lm3s9b96 in this case) and
// also the port control nibble required to enable that EPI signal.  The index
// into the array is the EPI signal number.
//
//*****************************************************************************
static const tEPIPinInfo g_psEPIPinInfo[NUM_EPI_SIGNALS] =
{
    {7, 8, 3},       // EPI0S00 on PH3
    {7, 8, 2},       // EPI0S01 on PH2
    {2, 8, 4},       // EPI0S02 on PC4
    {2, 8, 5},       // EPI0S03 on PC5
    {2, 8, 6},       // EPI0S04 on PC6
    {2, 8, 7},       // EPI0S05 on PC7
    {7, 8, 0},       // EPI0S06 on PH0
    {7, 8, 1},       // EPI0S07 on PH1
    {4, 8, 0},       // EPI0S08 on PE0
    {4, 8, 1},       // EPI0S09 on PE1
    {7, 8, 4},       // EPI0S10 on PH4
    {7, 8, 5},       // EPI0S11 on PH5
    {5, 8, 4},       // EPI0S12 on PF4
    {6, 8, 0},       // EPI0S13 on PG0
    {6, 8, 1},       // EPI0S14 on PG1
    {5, 8, 5},       // EPI0S15 on PF5
    {8, 8, 0},       // EPI0S16 on PJ0
    {8, 8, 1},       // EPI0S17 on PJ1
    {8, 8, 2},       // EPI0S18 on PJ2
    {8, 8, 3},       // EPI0S19 on PJ3
    {3, 8, 2},       // EPI0S20 on PD2
    {3, 8, 3},       // EPI0S21 on PD3
    {1, 8, 5},       // EPI0S22 on PB5
    {1, 8, 4},       // EPI0S23 on PB4
    {4, 8, 2},       // EPI0S24 on PE2
    {4, 8, 3},       // EPI0S25 on PE3
    {7, 8, 6},       // EPI0S26 on PH6
    {7, 8, 7},       // EPI0S27 on PH7
    {8, 8, 4},       // EPI0S28 on PJ4
    {8, 8, 5},       // EPI0S29 on PJ5
    {8, 8, 6},       // EPI0S30 on PJ6
    {6, 9, 7}        // EPI0S31 on PG7
};

//*****************************************************************************
//
// Bit mask defining the EPI signals (EPI0Snn, for 0 <= n < 32) required for
// the default configuration (in this case, we assume the SDRAM daughter board
// is present).
//
//*****************************************************************************
#define EPI_PINS_SDRAM 0xF00FFFFF

//*****************************************************************************
//
// I2C connections for the EEPROM device used on DK daughter boards to provide
// an ID to applications.
//
//*****************************************************************************
#define ID_I2C_PERIPH              (SYSCTL_PERIPH_I2C0)
#define ID_I2C_MASTER_BASE         (I2C0_MASTER_BASE)
#define ID_I2CSCL_GPIO_PERIPH      (SYSCTL_PERIPH_GPIOB)
#define ID_I2CSCL_GPIO_PORT        (GPIO_PORTB_BASE)
#define ID_I2CSCL_PIN              (GPIO_PIN_2)

#define ID_I2CSDA_GPIO_PERIPH      (SYSCTL_PERIPH_GPIOB)
#define ID_I2CSDA_GPIO_PORT        (GPIO_PORTB_BASE)
#define ID_I2CSDA_PIN              (GPIO_PIN_3)

#define ID_I2C_ADDR                0x50

//*****************************************************************************
//
// Reads from the I2C-attached EEPROM device.
//
// \param pucData points to storage for the data read from the EEPROM.
// \param ulOffset is the EEPROM address of the first byte to read.
// \param ulCount is the number of bytes of data to read from the EEPROM.
//
// This function reads one or more bytes of data from a given address in the
// ID EEPROM found on several of the lm3s9b96 development kit daughter boards.
// The return code indicates whether the read was successful.
//
// \return Returns \b true on success of \b false on failure.
//
//*****************************************************************************
static tBoolean
EEPROMReadPolled(unsigned char *pucData, unsigned long ulOffset,
                 unsigned long ulCount)
{
    unsigned long ulToRead;

    //
    // Clear any previously signalled interrupts.
    //
    I2CMasterIntClear(ID_I2C_MASTER_BASE);

    //
    // Start with a dummy write to get the address set in the EEPROM.
    //
    I2CMasterSlaveAddrSet(ID_I2C_MASTER_BASE, ID_I2C_ADDR, false);

    //
    // Place the address to be written in the data register.
    //
    I2CMasterDataPut(ID_I2C_MASTER_BASE, ulOffset);

    //
    // Perform a single send, writing the address as the only byte.
    //
    I2CMasterControl(ID_I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_START);

    //
    // Wait until the current byte has been transferred.
    //
    while(I2CMasterIntStatus(ID_I2C_MASTER_BASE, false) == 0)
    {
    }

    if(I2CMasterErr(ID_I2C_MASTER_BASE) != I2C_MASTER_ERR_NONE)
    {
        I2CMasterIntClear(ID_I2C_MASTER_BASE);
        return(false);
    }

    //
    // Clear any interrupts set.
    //
    I2CMasterIntClear(ID_I2C_MASTER_BASE);

    //
    // Put the I2C master into receive mode.
    //
    I2CMasterSlaveAddrSet(ID_I2C_MASTER_BASE, ID_I2C_ADDR, true);

    //
    // Start the receive.
    //
    I2CMasterControl(ID_I2C_MASTER_BASE,
                     ((ulCount > 1) ? I2C_MASTER_CMD_BURST_RECEIVE_START :
                     I2C_MASTER_CMD_SINGLE_RECEIVE));

    //
    // Receive the required number of bytes.
    //
    ulToRead = ulCount;

    while(ulToRead)
    {
        //
        // Wait until the current byte has been read.
        //
        //while(I2CMasterIntStatus(ID_I2C_MASTER_BASE, false) == 0)
        //{
        //}

        //
        // Read the received character.
        //
        *pucData++ = I2CMasterDataGet(ID_I2C_MASTER_BASE);
        ulToRead--;

        //
        // Clear pending interrupt notifications.
        //
        I2CMasterIntClear(ID_I2C_MASTER_BASE);

        //
        // Set up for the next byte if any more remain.
        //
        if(ulToRead)
        {
            I2CMasterControl(ID_I2C_MASTER_BASE,
                             ((ulToRead == 1) ?
                              I2C_MASTER_CMD_BURST_RECEIVE_FINISH :
                              I2C_MASTER_CMD_BURST_RECEIVE_CONT));
        }
    }

    //
    // Clear pending interrupt notification.
    //
    I2CMasterIntClear(ID_I2C_MASTER_BASE);

    //
    // Tell the caller we read the required data.