sal.h

讲述linux的初始化过程

	} slpi_bus_check_info[MAX_BUS_ERRORS];

	pal_min_state_area_t slpi_min_state_area;
	u64 slpi_br[8];
	u64 slpi_cr[128];
	u64 slpi_ar[128];
	u64 slpi_rr[8];
	u64 slpi_fr[128];
} sal_log_processor_info_t;

/* platform error log structures */
typedef struct platerr_logheader {
	u64 nextlog;		/* next log offset if present */
	u64 loglength;		/* log length */
	u64 logsubtype;		/* log subtype memory/bus/component */
	u64 eseverity;		/* error severity */
} ehdr_t;

typedef struct sysmem_errlog {
	ehdr_t lhdr;		/* header */
	u64 vflag;		/* valid bits for each field in the log */
	u64 addr;		/* memory address */
	u64 data;		/* memory data */
	u64 cmd;		/* command bus value if any */
	u64 ctrl;		/* control bus value if any */
	u64 addrsyndrome;	/* memory address ecc/parity syndrome bits */
	u64 datasyndrome;	/* data ecc/parity syndrome */
	u64 cacheinfo;		/* platform cache info as defined in pal spec. table 7-34 */
} merrlog_t;

typedef struct sysbus_errlog {
	ehdr_t lhdr;		/* linkded list header */
	u64 vflag;		/* valid bits for each field in the log */
	u64 busnum;		/* bus number in error */
	u64 reqaddr;		/* requestor address */
	u64 resaddr;		/* responder address */
	u64 taraddr;		/* target address */
	u64 data;		/* requester r/w data */
	u64 cmd;		/* bus commands */
	u64 ctrl;		/* bus controls (be# &-0) */
	u64 addrsyndrome;	/* addr bus ecc/parity bits */
	u64 datasyndrome;	/* data bus ecc/parity bits */
	u64 cmdsyndrome;	/* command bus ecc/parity bits */
	u64 ctrlsyndrome;	/* control bus ecc/parity bits */
} berrlog_t;

/* platform error log structures */
typedef struct syserr_chdr {	/* one header per component */
	u64 busnum;		/* bus number on which the component resides */
	u64 devnum;		/* same as device select */
	u64 funcid;		/* function id of the device */
	u64 devid;		/* pci device id */
	u64 classcode;		/* pci class code for the device */
	u64 cmdreg;		/* pci command reg value */
	u64 statreg;		/* pci status reg value */
} chdr_t;

typedef struct cfginfo {
	u64 cfgaddr;
	u64 cfgval;
} cfginfo_t;

typedef struct sys_comperr {	/* per component */
	ehdr_t lhdr;		/* linked list header */
	u64 vflag;		/* valid bits for each field in the log */
	chdr_t scomphdr;	
	u64 numregpair;		/* number of reg addr/value pairs */
	cfginfo_t cfginfo;
} cerrlog_t;

typedef struct sel_records {
	ehdr_t lhdr;
	u64 seldata;
} isel_t;

typedef struct plat_errlog {
	u64 mbcsvalid;		/* valid bits for each type of log */
	merrlog_t smemerrlog;	/* platform memory error logs */
	berrlog_t sbuserrlog;	/* platform bus error logs */
	cerrlog_t scomperrlog;	/* platform chipset error logs */
	isel_t selrecord;	/* ipmi sel record */
} platforminfo_t;

/* over all log structure (processor+platform) */

typedef union udev_specific_log {
	sal_log_processor_info_t proclog;
	platforminfo_t platlog;
} devicelog_t;


#define sal_log_processor_info_psi_valid		slpi_valid.spli_psi
#define sal_log_processor_info_cache_check_valid	slpi_valid.spli_cache_check
#define sal_log_processor_info_tlb_check_valid		slpi_valid.spli_tlb_check
#define sal_log_processor_info_bus_check_valid		slpi_valid.spli_bus_check
#define sal_log_processor_info_minstate_valid		slpi_valid.spli_minstate
#define sal_log_processor_info_bank1_gr_valid		slpi_valid.slpi_bank1_gr
#define sal_log_processor_info_br_valid			slpi_valid.slpi_br
#define sal_log_processor_info_cr_valid			slpi_valid.slpi_cr
#define sal_log_processor_info_ar_valid			slpi_valid.slpi_ar
#define sal_log_processor_info_rr_valid			slpi_valid.slpi_rr
#define sal_log_processor_info_fr_valid			slpi_valid.slpi_fr

typedef struct sal_log_header {
	u64 slh_next_log;	/* Offset of the next log from the beginning of this structure */
	u32 slh_log_len;	/* Length of this error log in bytes */
	u16 slh_log_type;	/* Type of log (0 - cpu ,1 - platform) */
	u16 slh_log_sub_type;	/* SGI specific sub type */
	sal_log_timestamp_t slh_log_timestamp;	/* Timestamp */
} sal_log_header_t;

/* SAL PSI log structure */
typedef struct psilog {
	sal_log_header_t sal_elog_header;
	devicelog_t devlog;
} ia64_psilog_t;

/*
 * Now define a couple of inline functions for improved type checking
 * and convenience.
 */
static inline long
ia64_sal_freq_base (unsigned long which, unsigned long *ticks_per_second,
		    unsigned long *drift_info)
{
	struct ia64_sal_retval isrv;

	SAL_CALL(isrv, SAL_FREQ_BASE, which, 0, 0, 0, 0, 0, 0);
	*ticks_per_second = isrv.v0;
	*drift_info = isrv.v1;
	return isrv.status;
}

/* Flush all the processor and platform level instruction and/or data caches */
static inline s64
ia64_sal_cache_flush (u64 cache_type)
{
	struct ia64_sal_retval isrv;
	SAL_CALL(isrv, SAL_CACHE_FLUSH, cache_type, 0, 0, 0, 0, 0, 0);
	return isrv.status;
}


	
/* Initialize all the processor and platform level instruction and data caches */
static inline s64
ia64_sal_cache_init (void)
{
	struct ia64_sal_retval isrv;
	SAL_CALL(isrv, SAL_CACHE_INIT, 0, 0, 0, 0, 0, 0, 0);
	return isrv.status;
}

/* Clear the processor and platform information logged by SAL with respect to the 
 * machine state at the time of MCA's, INITs or CMCs 
 */
static inline s64
ia64_sal_clear_state_info (u64 sal_info_type, u64 sal_info_sub_type)
{
	struct ia64_sal_retval isrv;
	SAL_CALL(isrv, SAL_CLEAR_STATE_INFO, sal_info_type, sal_info_sub_type,
	         0, 0, 0, 0, 0);
	return isrv.status;
}


/* Get the processor and platform information logged by SAL with respect to the machine
 * state at the time of the MCAs, INITs or CMCs.
 */
static inline u64
ia64_sal_get_state_info (u64 sal_info_type, u64 sal_info_sub_type, u64 *sal_info)
{
	struct ia64_sal_retval isrv;
	SAL_CALL(isrv, SAL_GET_STATE_INFO, sal_info_type, sal_info_sub_type,
	         sal_info, 0, 0, 0, 0);
	if (isrv.status)
		return 0;
	return isrv.v0;
}	
/* Get the maximum size of the information logged by SAL with respect to the machine 
 * state at the time of MCAs, INITs or CMCs
 */
static inline u64
ia64_sal_get_state_info_size (u64 sal_info_type, u64 sal_info_sub_type)
{
	struct ia64_sal_retval isrv;
	SAL_CALL(isrv, SAL_GET_STATE_INFO_SIZE, sal_info_type, sal_info_sub_type,
	         0, 0, 0, 0, 0);
	if (isrv.status)
		return 0;
	return isrv.v0;
}

/* Causes the processor to go into a spin loop within SAL where SAL awaits a wakeup
 * from the monarch processor.
 */
static inline s64
ia64_sal_mc_rendez (void)
{
	struct ia64_sal_retval isrv;
	SAL_CALL(isrv, SAL_MC_RENDEZ, 0, 0, 0, 0, 0, 0, 0);
	return isrv.status;
}

/* Allow the OS to specify the interrupt number to be used by SAL to interrupt OS during
 * the machine check rendezvous sequence as well as the mechanism to wake up the 
 * non-monarch processor at the end of machine check processing.
 */
static inline s64
ia64_sal_mc_set_params (u64 param_type, u64 i_or_m, u64 i_or_m_val, u64 timeout)
{
	struct ia64_sal_retval isrv;
	SAL_CALL(isrv, SAL_MC_SET_PARAMS, param_type, i_or_m, i_or_m_val, timeout,
	         0, 0, 0);
	return isrv.status;
}

/* Read from PCI configuration space */
static inline s64
ia64_sal_pci_config_read (u64 pci_config_addr, u64 size, u64 *value)
{
	struct ia64_sal_retval isrv;
	SAL_CALL(isrv, SAL_PCI_CONFIG_READ, pci_config_addr, size, 0, 0, 0, 0, 0);
	if (value)
		*value = isrv.v0;
	return isrv.status;
}

/* Write to PCI configuration space */
static inline s64
ia64_sal_pci_config_write (u64 pci_config_addr, u64 size, u64 value)
{
	struct ia64_sal_retval isrv;
	SAL_CALL(isrv, SAL_PCI_CONFIG_WRITE, pci_config_addr, size, value,
	         0, 0, 0, 0);
	return isrv.status;
}

/*
 * Register physical addresses of locations needed by SAL when SAL
 * procedures are invoked in virtual mode.
 */
static inline s64
ia64_sal_register_physical_addr (u64 phys_entry, u64 phys_addr)
{
	struct ia64_sal_retval isrv;
	SAL_CALL(isrv, SAL_REGISTER_PHYSICAL_ADDR, phys_entry, phys_addr,
	         0, 0, 0, 0, 0);
	return isrv.status;
}

/* Register software dependent code locations within SAL. These locations are handlers
 * or entry points where SAL will pass control for the specified event. These event
 * handlers are for the bott rendezvous, MCAs and INIT scenarios.
 */
static inline s64
ia64_sal_set_vectors (u64 vector_type,
		      u64 handler_addr1, u64 gp1, u64 handler_len1,
		      u64 handler_addr2, u64 gp2, u64 handler_len2)
{
	struct ia64_sal_retval isrv;
	SAL_CALL(isrv, SAL_SET_VECTORS, vector_type,
			handler_addr1, gp1, handler_len1,
			handler_addr2, gp2, handler_len2);			

	return isrv.status;
}		
/* Update the contents of PAL block in the non-volatile storage device */
static inline s64
ia64_sal_update_pal (u64 param_buf, u64 scratch_buf, u64 scratch_buf_size,
		     u64 *error_code, u64 *scratch_buf_size_needed)
{
	struct ia64_sal_retval isrv;
	SAL_CALL(isrv, SAL_UPDATE_PAL, param_buf, scratch_buf, scratch_buf_size,
	         0, 0, 0, 0);
	if (error_code)
		*error_code = isrv.v0;
	if (scratch_buf_size_needed)
		*scratch_buf_size_needed = isrv.v1;
	return isrv.status;
}

#endif /* _ASM_IA64_PAL_H */