horizon.h

讲述linux的初始化过程

/*
  Madge Horizon ATM Adapter driver.
  Copyright (C) 1995-1999  Madge Networks Ltd.

  This program is free software; you can redistribute it and/or modify
  it under the terms of the GNU General Public License as published by
  the Free Software Foundation; either version 2 of the License, or
  (at your option) any later version.

  This program is distributed in the hope that it will be useful,
  but WITHOUT ANY WARRANTY; without even the implied warranty of
  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  GNU General Public License for more details.

  You should have received a copy of the GNU General Public License
  along with this program; if not, write to the Free Software
  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

  The GNU GPL is contained in /usr/doc/copyright/GPL on a Debian
  system and in the file COPYING in the Linux kernel source.
*/

/*
  IMPORTANT NOTE: Madge Networks no longer makes the adapters
  supported by this driver and makes no commitment to maintain it.
*/

/* too many macros - change to inline functions */

#ifndef DRIVER_ATM_HORIZON_H
#define DRIVER_ATM_HORIZON_H

#include <linux/config.h>
#include <linux/version.h>

#ifdef CONFIG_ATM_HORIZON_DEBUG
#define DEBUG_HORIZON
#endif

#define DEV_LABEL                         "hrz"

#ifndef PCI_VENDOR_ID_MADGE
#define PCI_VENDOR_ID_MADGE               0x10B6
#endif
#ifndef PCI_DEVICE_ID_MADGE_HORIZON
#define PCI_DEVICE_ID_MADGE_HORIZON       0x1000
#endif

// diagnostic output

#define PRINTK(severity,format,args...) \
  printk(severity DEV_LABEL ": " format "\n" , ## args)

#ifdef DEBUG_HORIZON

#define DBG_ERR  0x0001
#define DBG_WARN 0x0002
#define DBG_INFO 0x0004
#define DBG_VCC  0x0008
#define DBG_QOS  0x0010
#define DBG_TX   0x0020
#define DBG_RX   0x0040
#define DBG_SKB  0x0080
#define DBG_IRQ  0x0100
#define DBG_FLOW 0x0200
#define DBG_BUS  0x0400
#define DBG_REGS 0x0800
#define DBG_DATA 0x1000
#define DBG_MASK 0x1fff

/* the ## prevents the annoying double expansion of the macro arguments */
/* KERN_INFO is used since KERN_DEBUG often does not make it to the console */
#define PRINTDB(bits,format,args...) \
  ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format , ## args) : 1 )
#define PRINTDM(bits,format,args...) \
  ( (debug & (bits)) ? printk (format , ## args) : 1 )
#define PRINTDE(bits,format,args...) \
  ( (debug & (bits)) ? printk (format "\n" , ## args) : 1 )
#define PRINTD(bits,format,args...) \
  ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format "\n" , ## args) : 1 )

#else

#define PRINTD(bits,format,args...)
#define PRINTDB(bits,format,args...)
#define PRINTDM(bits,format,args...)
#define PRINTDE(bits,format,args...)

#endif

#define PRINTDD(sec,fmt,args...)
#define PRINTDDB(sec,fmt,args...)
#define PRINTDDM(sec,fmt,args...)
#define PRINTDDE(sec,fmt,args...)

// fixed constants

#define SPARE_BUFFER_POOL_SIZE            MAX_VCS
#define HRZ_MAX_VPI                       4
#define MIN_PCI_LATENCY                   48 // 24 IS TOO SMALL

/*  Horizon specific bits */
/*  Register offsets */

#define HRZ_IO_EXTENT                     0x80

#define DATA_PORT_OFF                     0x00
#define TX_CHANNEL_PORT_OFF               0x04
#define TX_DESCRIPTOR_PORT_OFF            0x08
#define MEMORY_PORT_OFF                   0x0C
#define MEM_WR_ADDR_REG_OFF               0x14
#define MEM_RD_ADDR_REG_OFF               0x18
#define CONTROL_0_REG                     0x1C
#define INT_SOURCE_REG_OFF                0x20
#define INT_ENABLE_REG_OFF                0x24
#define MASTER_RX_ADDR_REG_OFF            0x28
#define MASTER_RX_COUNT_REG_OFF           0x2C
#define MASTER_TX_ADDR_REG_OFF            0x30
#define MASTER_TX_COUNT_REG_OFF           0x34
#define TX_DESCRIPTOR_REG_OFF             0x38
#define TX_CHANNEL_CONFIG_COMMAND_OFF     0x40
#define TX_CHANNEL_CONFIG_DATA_OFF        0x44
#define TX_FREE_BUFFER_COUNT_OFF          0x48
#define RX_FREE_BUFFER_COUNT_OFF          0x4C
#define TX_CONFIG_OFF                     0x50
#define TX_STATUS_OFF                     0x54
#define RX_CONFIG_OFF                     0x58
#define RX_LINE_CONFIG_OFF                0x5C
#define RX_QUEUE_RD_PTR_OFF               0x60
#define RX_QUEUE_WR_PTR_OFF               0x64
#define MAX_AAL5_CELL_COUNT_OFF           0x68
#define RX_CHANNEL_PORT_OFF               0x6C
#define TX_CELL_COUNT_OFF                 0x70
#define RX_CELL_COUNT_OFF                 0x74
#define HEC_ERROR_COUNT_OFF               0x78
#define UNASSIGNED_CELL_COUNT_OFF         0x7C

/*  Register bit definitions */

/* Control 0 register */

#define SEEPROM_DO                        0x00000001
#define SEEPROM_DI                        0x00000002
#define SEEPROM_SK                        0x00000004
#define SEEPROM_CS                        0x00000008
#define DEBUG_BIT_0                       0x00000010
#define DEBUG_BIT_1                       0x00000020
#define DEBUG_BIT_2                       0x00000040
//      RESERVED                          0x00000080
#define DEBUG_BIT_0_OE                    0x00000100
#define DEBUG_BIT_1_OE                    0x00000200
#define DEBUG_BIT_2_OE                    0x00000400
//      RESERVED                          0x00000800
#define DEBUG_BIT_0_STATE                 0x00001000
#define DEBUG_BIT_1_STATE                 0x00002000
#define DEBUG_BIT_2_STATE                 0x00004000
//      RESERVED                          0x00008000
#define GENERAL_BIT_0                     0x00010000
#define GENERAL_BIT_1                     0x00020000
#define GENERAL_BIT_2                     0x00040000
#define GENERAL_BIT_3                     0x00080000
#define RESET_HORIZON                     0x00100000
#define RESET_ATM                         0x00200000
#define RESET_RX                          0x00400000
#define RESET_TX                          0x00800000
#define RESET_HOST                        0x01000000
//      RESERVED                          0x02000000
#define TARGET_RETRY_DISABLE              0x04000000
#define ATM_LAYER_SELECT                  0x08000000
#define ATM_LAYER_STATUS                  0x10000000
//      RESERVED                          0xE0000000

/* Interrupt source and enable registers */

#define RX_DATA_AV                        0x00000001
#define RX_DISABLED                       0x00000002
#define TIMING_MARKER                     0x00000004
#define FORCED                            0x00000008
#define RX_BUS_MASTER_COMPLETE            0x00000010
#define TX_BUS_MASTER_COMPLETE            0x00000020
#define ABR_TX_CELL_COUNT_INT             0x00000040
#define DEBUG_INT                         0x00000080
//      RESERVED                          0xFFFFFF00

/* PIO and Bus Mastering */

#define MAX_PIO_COUNT                     0x000000ff // 255 - make tunable?
// 8188 is a hard limit for bus mastering
#define MAX_TRANSFER_COUNT                0x00001ffc // 8188
#define MASTER_TX_AUTO_APPEND_DESC        0x80000000

/* TX channel config command port */

#define PCR_TIMER_ACCESS                      0x0000
#define SCR_TIMER_ACCESS                      0x0001
#define BUCKET_CAPACITY_ACCESS                0x0002
#define BUCKET_FULLNESS_ACCESS                0x0003
#define RATE_TYPE_ACCESS                      0x0004
//      UNUSED                                0x00F8
#define TX_CHANNEL_CONFIG_MULT                0x0100
//      UNUSED                                0xF800
#define BUCKET_MAX_SIZE                       0x003f

/* TX channel config data port */

#define CLOCK_SELECT_SHIFT                    4
#define CLOCK_DISABLE                         0x00ff

#define IDLE_RATE_TYPE                       0x0
#define ABR_RATE_TYPE                        0x1
#define VBR_RATE_TYPE                        0x2
#define CBR_RATE_TYPE                        0x3

/* TX config register */

#define DRVR_DRVRBAR_ENABLE                   0x0001
#define TXCLK_MUX_SELECT_RCLK                 0x0002
#define TRANSMIT_TIMING_MARKER                0x0004
#define LOOPBACK_TIMING_MARKER                0x0008
#define TX_TEST_MODE_16MHz                    0x0000
#define TX_TEST_MODE_8MHz                     0x0010
#define TX_TEST_MODE_5_33MHz                  0x0020
#define TX_TEST_MODE_4MHz                     0x0030
#define TX_TEST_MODE_3_2MHz                   0x0040
#define TX_TEST_MODE_2_66MHz                  0x0050
#define TX_TEST_MODE_2_29MHz                  0x0060
#define TX_NORMAL_OPERATION                   0x0070
#define ABR_ROUND_ROBIN                       0x0080

/* TX status register */

#define IDLE_CHANNELS_MASK                    0x00FF
#define ABR_CELL_COUNT_REACHED_MULT           0x0100 
#define ABR_CELL_COUNT_REACHED_MASK           0xFF

/* RX config register */

#define NON_USER_CELLS_IN_ONE_CHANNEL         0x0008
#define RX_ENABLE                             0x0010
#define IGNORE_UNUSED_VPI_VCI_BITS_SET        0x0000
#define NON_USER_UNUSED_VPI_VCI_BITS_SET      0x0020
#define DISCARD_UNUSED_VPI_VCI_BITS_SET       0x0040

/* RX line config register */

#define SIGNAL_LOSS                           0x0001
#define FREQUENCY_DETECT_ERROR                0x0002
#define LOCK_DETECT_ERROR                     0x0004
#define SELECT_INTERNAL_LOOPBACK              0x0008
#define LOCK_DETECT_ENABLE                    0x0010
#define FREQUENCY_DETECT_ENABLE               0x0020
#define USER_FRAQ                             0x0040
#define GXTALOUT_SELECT_DIV4                  0x0080
#define GXTALOUT_SELECT_NO_GATING             0x0100
#define TIMING_MARKER_RECEIVED                0x0200

/* RX channel port */