cirrus.h

讲述linux的初始化过程

/****************************************************************************
 *******                                                              *******
 *******		CIRRUS.H				      *******
 *******                                                              *******
 ****************************************************************************

 Author  : Jeremy Rolls
 Date    : 3 Aug 1990

 *
 *  (C) 1990 - 2000 Specialix International Ltd., Byfleet, Surrey, UK.
 *
 *      This program is free software; you can redistribute it and/or modify
 *      it under the terms of the GNU General Public License as published by
 *      the Free Software Foundation; either version 2 of the License, or
 *      (at your option) any later version.
 *
 *      This program is distributed in the hope that it will be useful,
 *      but WITHOUT ANY WARRANTY; without even the implied warranty of
 *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *      GNU General Public License for more details.
 *
 *      You should have received a copy of the GNU General Public License
 *      along with this program; if not, write to the Free Software
 *      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

 Version : 0.01


                            Mods
 ----------------------------------------------------------------------------
  Date     By                Description
 ----------------------------------------------------------------------------

 ***************************************************************************/

#ifndef _cirrus_h
#ifndef lint
/* static char* _cirrus_h_sccs = "@(#)cirrus.h	1.16"; */
#endif
#define _cirrus_h 1

#ifdef RTA
#define	TO_UART	RX
#define TO_DRIVER TX
#endif

#ifdef HOST
#define	TO_UART	TX
#define TO_DRIVER RX
#endif
#ifdef RTA
/* Miscellaneous defines for CIRRUS addresses and related logic for
   interrupts etc.
*/
#define	MAP(a)		((short *)(cirrus_base + (a)))
#define outp(a,b)	(*MAP (a) =(b))
#define inp(a)		((*MAP (a)) & 0xff)
#define	CIRRUS_FIRST	(short*)0x7300
#define	CIRRUS_SECOND	(short*)0x7200
#define	CIRRUS_THIRD	(short*)0x7100
#define	CIRRUS_FOURTH	(short*)0x7000
#define	PORTS_ON_CIRRUS	4
#define	CIRRUS_FIFO_SIZE	12
#define	SPACE		0x20
#define	TAB		0x09
#define	LINE_FEED	0x0a
#define	CARRIAGE_RETURN	0x0d
#define	BACKSPACE	0x08
#define	SPACES_IN_TABS	8
#define	SEND_ESCAPE	0x00
#define START_BREAK	0x81
#define	TIMER_TICK	0x82
#define STOP_BREAK	0x83
#define BASE(a) ((a) < 4 ? (short*)CIRRUS_FIRST : ((a) < 8 ? (short *)CIRRUS_SECOND : ((a) < 12 ? (short*)CIRRUS_THIRD : (short *)CIRRUS_FOURTH)))
#define txack1	((short *)0x7104) 
#define rxack1	((short *)0x7102) 
#define mdack1  ((short *)0x7106)
#define txack2  ((short *)0x7006) 
#define rxack2	((short *)0x7004) 
#define mdack2  ((short *)0x7100) 
#define int_latch       ((short *) 0x7800)
#define int_status      ((short *) 0x7c00) 
#define tx1_pending     0x20 
#define rx1_pending     0x10 
#define md1_pending     0x40 
#define tx2_pending     0x02 
#define rx2_pending     0x01 
#define md2_pending     0x40 
#define module1_bits	0x07
#define module1_modern	0x08
#define module2_bits	0x70
#define module2_modern	0x80
#define module_blank	0xf
#define rs232_d25	0x0
#define	rs232_rj45	0x1
#define rs422_d25	0x3
#define parallel	0x5

#define	CLK0	0x00
#define CLK1	0x01
#define CLK2	0x02
#define CLK3	0x03
#define CLK4	0x04

#define CIRRUS_REVC    0x42
#define CIRRUS_REVE    0x44

#define	TURNON	1
#define TURNOFF 0

/* The list of CIRRUS registers. 
   NB. These registers are relative values on 8 bit boundaries whereas
   on the RTA's the CIRRUS registers are on word boundaries. Use pointer
   arithmetic (short *) to obtain the real addresses required */
#define ccr	0x05	/* Channel Command Register     */
#define ier	0x06	/* Interrupt Enable Register    */
#define cor1	0x08	/* Channel Option Register 1    */
#define cor2	0x09	/* Channel Option Register 2    */
#define cor3	0x0a	/* Channel Option Register 3    */
#define cor4	0x1e	/* Channel Option Register 4    */
#define	cor5	0x1f	/* Channel Option Register 5	*/

#define ccsr	0x0b	/* Channel Control Status Register */
#define rdcr	0x0e	/* Receive Data Count Register  */
#define tdcr	0x12	/* Transmit Data Count Register */
#define mcor1	0x15	/* Modem Change Option Register 1 */
#define mcor2	0x16	/* Modem Change Option Regsiter 2 */

#define livr	0x18	/* Local Interrupt Vector Register */
#define schr1	0x1a	/* Special Character Register 1 */
#define schr2	0x1b	/* Special Character Register 2 */
#define schr3	0x1c	/* Special Character Register 3 */
#define schr4	0x1d	/* Special Character Register 4 */

#define rtr	0x20    /* Receive Timer Register */
#define rtpr	0x21	/* Receive Timeout Period Register */
#define lnc	0x24	/* Lnext character */

#define rivr	0x43	/* Receive Interrupt Vector Register    */
#define tivr	0x42	/* Transmit Interrupt Vector Register   */
#define mivr	0x41	/* Modem Interrupt Vector Register      */
#define gfrcr	0x40	/* Global Firmware Revision code Reg    */
#define ricr	0x44	/* Receive Interrupting Channel Reg     */
#define ticr	0x45	/* Transmit Interrupting Channel Reg    */
#define micr	0x46	/* Modem Interrupting Channel Register  */

#define gcr	0x4b	/* Global configuration register*/
#define misr    0x4c    /* Modem interrupt status register */

#define rbusr	0x59
#define tbusr	0x5a
#define mbusr	0x5b

#define eoir	0x60	/* End Of Interrupt Register */
#define rdsr	0x62	/* Receive Data / Status Register */
#define tdr	0x63	/* Transmit Data Register */
#define svrr	0x67	/* Service Request Register */

#define car	0x68	/* Channel Access Register */
#define mir	0x69	/* Modem Interrupt Register */
#define tir	0x6a	/* Transmit Interrupt Register */
#define rir	0x6b	/* Receive Interrupt Register */
#define msvr1	0x6c	/* Modem Signal Value Register 1 */
#define msvr2	0x6d	/* Modem Signal Value Register 2*/
#define psvr	0x6f	/* Printer Signal Value Register*/

#define tbpr	0x72	/* Transmit Baud Rate Period Register */
#define tcor	0x76	/* Transmit Clock Option Register */

#define rbpr	0x78	/* Receive Baud Rate Period Register */
#define rber	0x7a	/* Receive Baud Rate Extension Register */
#define rcor	0x7c	/* Receive Clock Option Register*/
#define ppr	0x7e	/* Prescalar Period Register    */

/* Misc registers used for forcing the 1400 out of its reset woes */
#define airl	0x6d
#define airm	0x6e
#define airh	0x6f
#define btcr	0x66
#define mtcr	0x6c
#define tber	0x74

#endif				/* #ifdef RTA */


/* Bit fields for particular registers */

/* GCR */
#define GCR_SERIAL	0x00	/* Configure as serial channel */
#define GCR_PARALLEL	0x80	/* Configure as parallel channel */

/* RDSR - when status read from FIFO */
#define	RDSR_BREAK		0x08	/* Break received */
#define RDSR_TIMEOUT    	0x80    /* No new data timeout */
#define RDSR_SC1  	  	0x10    /* Special char 1 (tx XON) matched */
#define RDSR_SC2  	  	0x20    /* Special char 2 (tx XOFF) matched */
#define RDSR_SC12_MASK	  	0x30    /* Mask for special chars 1 and 2 */

/* PPR */
#define PPR_DEFAULT	0x31	/* Default value - for a 25Mhz clock gives
				   a timeout period of 1ms */

/* LIVR */
#define	LIVR_EXCEPTION	0x07	/* Receive exception interrupt */

/* CCR */
#define	CCR_RESET	0x80	/* Reset channel */
#define	CCR_CHANGE	0x4e	/* COR's have changed - NB always change all
				   COR's */
#define	CCR_WFLUSH	0x82	/* Flush transmit FIFO and TSR / THR */

#define	CCR_SENDSC1	0x21	/* Send special character one */
#define CCR_SENDSC2	0x22	/* Send special character two */
#define CCR_SENDSC3	0x23	/* Send special character three */
#define CCR_SENDSC4	0x24	/* Send special character four */

#define CCR_TENABLE	0x18	/* Enable transmitter */
#define	CCR_TDISABLE	0x14	/* Disable transmitter */
#define CCR_RENABLE	0x12	/* Enable receiver */
#define CCR_RDISABLE	0x11	/* Disable receiver */

#define	CCR_READY	0x00	/* CCR is ready for another command */

/* CCSR */
#define CCSR_TXENABLE	0x08	/* Transmitter enable */
#define CCSR_RXENABLE	0x80	/* Receiver enable */
#define CCSR_TXFLOWOFF	0x04	/* Transmit flow off */
#define CCSR_TXFLOWON	0x02	/* Transmit flow on */

/* SVRR */
#define	SVRR_RECEIVE	0x01	/* Receive interrupt pending */