head_4xx.s

讲述linux的初始化过程

	li	r7,STND_EXC		# This is a standard exception
	li	r20,MSR_KERNEL
	rlwimi	r20,r23,0,16,16		# Copy EE bit from the saved MSR
	FINISH_EXCEPTION(ProgramCheckException)
	
	STND_EXCEPTION(0x0800,	Trap_08,		UnknownException)
	STND_EXCEPTION(0x0900,	Trap_09,		UnknownException)
	STND_EXCEPTION(0x0A00,	Trap_0A,		UnknownException)
	STND_EXCEPTION(0x0B00,	Trap_0B,		UnknownException)		
### 0x0C00 - System Call Exception

	START_EXCEPTION(0x0C00,	SystemCall)
	STND_EXCEPTION_PROLOG
	stw	r3,ORIG_GPR3(r21)
	li	r7,STND_EXC		# This is a standard exception
	li	r20,MSR_KERNEL
	rlwimi	r20,r23,0,16,16		# Copy EE bit from the saved MSR
	FINISH_EXCEPTION(DoSyscall)

	STND_EXCEPTION(0x0D00,	Trap_0D,		UnknownException)
	STND_EXCEPTION(0x0E00,	Trap_0E,		UnknownException)
	STND_EXCEPTION(0x0F00,	Trap_0F,		UnknownException)

### 0x1000 - Programmable Interval Timer (PIT) Exception

	START_EXCEPTION(0x1000,	Decrementer)
	STND_EXCEPTION_PROLOG
	lis	r0,TSR_PIS@h		# Set-up the PIT exception mask
	mtspr	SPRN_TSR,r0		# Clear the PIT exception
	addi	r3,r1,STACK_FRAME_OVERHEAD
	li	r7,STND_EXC		# This is a standard exception
	li	r20,MSR_KERNEL
	bl	transfer_to_handler
_GLOBAL(timer_interrupt_intercept)
	.long	timer_interrupt
	.long	ret_from_intercept

#if 0
### 0x1010 - Fixed Interval Timer (FIT) Exception
	
	STND_EXCEPTION(0x1010,	FITException,		UnknownException)

### 0x1020 - Watchdog Timer (WDT) Exception

	CRIT_EXCEPTION(0x1020,	WDTException,		UnknownException)
#endif

### 0x1100 - Data TLB Miss Exception

	STND_EXCEPTION(0x1100,	DTLBMiss, 		PPC4xx_dtlb_miss)

### 0x1200 - Instruction TLB Miss Exception

	STND_EXCEPTION(0x1200,	ITLBMiss, 		PPC4xx_itlb_miss)

	STND_EXCEPTION(0x1300,	Trap_13,		UnknownException)
	STND_EXCEPTION(0x1400,	Trap_14,		UnknownException)
	STND_EXCEPTION(0x1500,	Trap_15,		UnknownException)
	STND_EXCEPTION(0x1600,	Trap_16,		UnknownException)
	STND_EXCEPTION(0x1700,	Trap_17,		UnknownException)
	STND_EXCEPTION(0x1800,	Trap_18,		UnknownException)
	STND_EXCEPTION(0x1900,	Trap_19,		UnknownException)
	STND_EXCEPTION(0x1A00,	Trap_1A,		UnknownException)
	STND_EXCEPTION(0x1B00,	Trap_1B,		UnknownException)
	STND_EXCEPTION(0x1C00,	Trap_1C,		UnknownException)
	STND_EXCEPTION(0x1D00,	Trap_1D,		UnknownException)
	STND_EXCEPTION(0x1E00,	Trap_1E,		UnknownException)
	STND_EXCEPTION(0x1F00,	Trap_1F,		UnknownException)
	
### 0x2000 - Debug Exception

	CRIT_EXCEPTION(0x2000,	DebugTrap,		UnknownException)

###
### Other PowerPC processors, namely those derived from the 6xx-series
### have vectors from 0x2100 through 0x2F00 defined, but marked as reserved.
### However, for the 4xx-series processors these are neither defined nor
### reserved.
### 

### 
### This code finishes saving the registers to the exception frame
### and jumps to the appropriate handler for the exception, turning
### on address translation.
###

_GLOBAL(transfer_to_handler)
	stw	r22,_NIP(r21)		# Save the faulting IP on the stack
	stw	r23,_MSR(r21)		# Save the exception MSR on the stack
	SAVE_4GPRS(8, r21)		# Save r8 through r11 on the stack
	SAVE_8GPRS(12, r21)		# Save r12 through r19 on the stack
	SAVE_8GPRS(24, r21)		# Save r24 through r31 on the stack
	andi.	r23,r23,MSR_PR		# Is this from user space?
	mfspr	r23,SPRN_SPRG3		# If from user, fix up THREAD.regs
	beq	2f			# No, it is from the kernel; branch.
	addi	r24,r1,STACK_FRAME_OVERHEAD
	stw	r24,PT_REGS(r23)	# 
2:	addi	r2,r23,-THREAD		# Set r2 to current thread
	tovirt(r2,r2)
	mflr	r23
	andi.	r24,r23,0x3f00		# Get vector offset
	stw	r24,TRAP(r21)
	li	r22,RESULT
	stwcx.	r22,r22,r21		# Clear the reservation
	li	r22,0
	stw	r22,RESULT(r21)
	mtspr	SPRN_SPRG2,r22		# r1 is now the kernel stack pointer
	addi	r24,r2,TASK_STRUCT_SIZE	# Check for kernel stack overflow
	cmplw	cr0,r1,r2
	cmplw	cr1,r1,r24
	crand	cr1,cr1,cr4
	bgt-	stack_ovf		# If r2 < r1 < r2 + TASK_STRUCT_SIZE
	lwz	r24,0(r23)		# Virtual address of the handler
	lwz	r23,4(r23)		# Handler return pointer
	cmpwi	cr0,r7,STND_EXC		# What type of exception is this?
	bne	3f			# It is a critical exception...

	## Standard exception jump path
	
	mtspr	SPRN_SRR0,r24		# Set up the instruction pointer
	mtspr	SPRN_SRR1,r20		# Set up the machine state register
	mtlr	r23			# Set up the return pointer
	SYNC
	rfi				# Enable the MMU, jump to the handler

	## Critical exception jump path

3:	mtspr	SPRN_SRR2,r24		# Set up the instruction pointer
	mtspr	SPRN_SRR3,r20		# Set up the machine state register
	mtlr	r23			# Set up the return pointer
	SYNC
	rfci				# Enable the MMU, jump to the handler

###
### On kernel stack overlow, load up an initial stack pointer and call
### StackOverflow(regs), which should NOT return.
### 

stack_ovf:
	addi	r3,r1,STACK_FRAME_OVERHEAD
	lis	r1,init_task_union@ha
	addi	r1,r1,init_task_union@l
	addi	r1,r1,TASK_UNION_SIZE - STACK_FRAME_OVERHEAD
	lis	r24,StackOverflow@ha
	addi	r24,r24,StackOverflow@l
	li	r20,MSR_KERNEL
	mtspr	SPRN_SRR0,r24		# Set up the instruction pointer
	mtspr	SPRN_SRR1,r20		# Set up the machine state register
	SYNC
	rfi				# Enable the MMU, jump to StackOverflow

###
### extern void giveup_altivec(struct task_struct *prev)
###
### The PowerPC 4xx family of processors do not have AltiVec capabilities, so
### this just returns.
###

_GLOBAL(giveup_altivec)
	blr
	
###
### extern void giveup_fpu(struct task_struct *prev)
###
### The PowerPC 4xx family of processors do not have an FPU, so this just
### returns.
###

_GLOBAL(giveup_fpu)
	blr

###
### extern void abort(void)
###
### At present, this routine just applies a system reset.
### 
	
_GLOBAL(abort)
	mfspr	r13,SPRN_DBCR
	oris	r13,r13,DBCR_RST(DBCR_RST_SYSTEM)@h
	mtspr	SPRN_DBCR,r13


### 
### This is where the main kernel code starts.
### 

start_here:
	## Establish a pointer to the current task
	
	lis	r2,init_task_union@h
	ori	r2,r2,init_task_union@l
	
	## Clear out the BSS as per ANSI C requirements

	lis	r7,_end@ha
	addi	r7,r7,_end@l
	lis	r8,__bss_start@ha
	addi	r8,r8,__bss_start@l
	subf	r7,r8,r7
	addi	r7,r7,3
	srwi.	r7,r7,2
	beq	2f
	addi	r8,r8,-4
	mtctr	r7
	li	r0,0
3:	stwu	r0,4(r8)
	bdnz	3b

	## Stack
	
2:	addi	r1,r2,TASK_UNION_SIZE
	li	r0,0
	stwu	r0,-STACK_FRAME_OVERHEAD(r1)

	## Determine what type of platform this is.

	mr	r3,r31
	mr	r4,r30
	mr	r5,r29
	mr	r6,r28
	mr	r7,r27
	bl	identify_machine
	
	## Initialize the memory management unit.

	bl	MMU_init

	## Go back to running unmapped so that we can change to our
	## exception vectors.

	lis	r4,2f@h
	ori	r4,r4,2f@l
	tophys(r4,r4)
	li	r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
	mtspr	SPRN_SRR0,r4		# Set up the instruction pointer
	mtspr	SPRN_SRR1,r3		# Set up the machine state register
	rfi

	## Load up the kernel context

2:	SYNC				# Force all PTE updates to finish
#	tlbia				# Clear all TLB entries
#	sync				# Wait for tlbia to finish...

	## Set up for using our exception vectors
	
	tophys(r4,r2)			# Pointer to physical current thread
	addi	r4,r4,THREAD		# The init task thread
	mtspr	SPRN_SPRG3,r4		# Save it for exceptions later
	li	r3,0			# 
	mtspr	SPRN_SPRG2,r3		# 0 implies r1 has kernel stack pointer
	
	## Really turn on the MMU and jump into the kernel

        lis     r4,MSR_KERNEL@h
        ori     r4,r4,MSR_KERNEL@l
        lis     r3,start_kernel@h
        ori     r3,r3,start_kernel@l
        mtspr   SPRN_SRR0,r3		# Set up the instruction pointer
        mtspr   SPRN_SRR1,r4		# Set up the machine state register
        rfi				# Enable the MMU, jump to the kernel

_GLOBAL(set_context)
	mtspr	SPRN_PID,r3
	blr

###
### We put a few things here that have to be page-aligned. This stuff
### goes at the beginning of the data segment, which is page-aligned.
###

	.data
_GLOBAL(sdata)
_GLOBAL(empty_zero_page)
	.space	4096
_GLOBAL(swapper_pg_dir)
	.space	4096	

###
### This space gets a copy of optional info passed to us by the bootstrap
### which is used to pass parameters into the kernel like root=/dev/sda1, etc.
###

_GLOBAL(cmd_line)
	.space	512