pci_common.c

讲述linux的初始化过程

			cmd |= PCI_COMMAND_IO;
		if (mem_seen)
			cmd |= PCI_COMMAND_MEMORY;
		pci_write_config_word(pdev, PCI_COMMAND, cmd);
	}

	/* If this is a PCI bridge or an IDE controller,
	 * enable bus mastering.  In the former case also
	 * set the cache line size correctly.
	 */
	if (((pdev->class >> 8) == PCI_CLASS_BRIDGE_PCI) ||
	    (((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) &&
	     ((pdev->class & 0x80) != 0))) {
		pci_read_config_word(pdev, PCI_COMMAND, &cmd);
		cmd |= PCI_COMMAND_MASTER;
		pci_write_config_word(pdev, PCI_COMMAND, cmd);

		if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
			pci_write_config_byte(pdev,
					      PCI_CACHE_LINE_SIZE,
					      (64 / sizeof(u32)));
	}
}

void __init pci_assign_unassigned(struct pci_pbm_info *pbm,
				  struct pci_bus *pbus)
{
	struct list_head *walk = &pbus->devices;

	for (walk = walk->next; walk != &pbus->devices; walk = walk->next)
		pdev_assign_unassigned(pbm, pci_dev_b(walk));

	walk = &pbus->children;
	for (walk = walk->next; walk != &pbus->children; walk = walk->next)
		pci_assign_unassigned(pbm, pci_bus_b(walk));
}

static int __init pci_intmap_match(struct pci_dev *pdev, unsigned int *interrupt)
{
	struct pcidev_cookie *dev_pcp = pdev->sysdata;
	struct pci_pbm_info *pbm = dev_pcp->pbm;
	struct linux_prom_pci_registers *pregs = dev_pcp->prom_regs;
	unsigned int hi, mid, lo, irq;
	int i;

	if (pbm->num_pbm_intmap == 0)
		return 0;

	/* If we are underneath a PCI bridge, use PROM register
	 * property of the parent bridge which is closest to
	 * the PBM.
	 */
	if (pdev->bus->number != pbm->pci_first_busno) {
		struct pcidev_cookie *bus_pcp;
		struct pci_dev *pwalk;
		int offset;

		pwalk = pdev->bus->self;
		while (pwalk->bus &&
		       pwalk->bus->number != pbm->pci_first_busno)
			pwalk = pwalk->bus->self;

		bus_pcp = pwalk->sysdata;
		pregs = bus_pcp->prom_regs;

		offset = prom_getint(dev_pcp->prom_node,
				     "fcode-rom-offset");

		/* Did PROM know better and assign an interrupt other
		 * than #INTA to the device? - We test here for presence of
		 * FCODE on the card, in this case we assume PROM has set
		 * correct 'interrupts' property, unless it is quadhme.
		 */
		if (offset == -1 ||
		    !strcmp(dev_pcp->prom_name, "SUNW,qfe") ||
		    !strcmp(dev_pcp->prom_name, "qfe")) {
			/*
			 * No, use low slot number bits of child as IRQ line.
			 */
			*interrupt = ((*interrupt - 1 + PCI_SLOT(pdev->devfn)) & 3) + 1;
		}
	}

	hi   = pregs->phys_hi & pbm->pbm_intmask.phys_hi;
	mid  = pregs->phys_mid & pbm->pbm_intmask.phys_mid;
	lo   = pregs->phys_lo & pbm->pbm_intmask.phys_lo;
	irq  = *interrupt & pbm->pbm_intmask.interrupt;

	for (i = 0; i < pbm->num_pbm_intmap; i++) {
		if (pbm->pbm_intmap[i].phys_hi  == hi	&&
		    pbm->pbm_intmap[i].phys_mid == mid	&&
		    pbm->pbm_intmap[i].phys_lo  == lo	&&
		    pbm->pbm_intmap[i].interrupt == irq) {
			*interrupt = pbm->pbm_intmap[i].cinterrupt;
			return 1;
		}
	}

	prom_printf("pbm_intmap_match: bus %02x, devfn %02x: ",
		    pdev->bus->number, pdev->devfn);
	prom_printf("IRQ [%08x.%08x.%08x.%08x] not found in interrupt-map\n",
		    pregs->phys_hi, pregs->phys_mid, pregs->phys_lo, *interrupt);
	prom_printf("Please email this information to [e-mail]\n");
	prom_halt();
}

static void __init pdev_fixup_irq(struct pci_dev *pdev)
{
	struct pcidev_cookie *pcp = pdev->sysdata;
	struct pci_pbm_info *pbm = pcp->pbm;
	struct pci_controller_info *p = pbm->parent;
	unsigned int portid = p->portid;
	unsigned int prom_irq;
	int prom_node = pcp->prom_node;
	int err;

	err = prom_getproperty(prom_node, "interrupts",
			       (char *)&prom_irq, sizeof(prom_irq));
	if (err == 0 || err == -1) {
		pdev->irq = 0;
		return;
	}

	/* Fully specified already? */
	if (((prom_irq & PCI_IRQ_IGN) >> 6) == portid) {
		pdev->irq = p->irq_build(p, pdev, prom_irq);
		goto have_irq;
	}

	/* An onboard device? (bit 5 set) */
	if ((prom_irq & PCI_IRQ_INO) & 0x20) {
		pdev->irq = p->irq_build(p, pdev, (portid << 6 | prom_irq));
		goto have_irq;
	}

	/* Can we find a matching entry in the interrupt-map? */
	if (pci_intmap_match(pdev, &prom_irq)) {
		pdev->irq = p->irq_build(p, pdev, (portid << 6) | prom_irq);
		goto have_irq;
	}

	/* Ok, we have to do it the hard way. */
	{
		unsigned int bus, slot, line;

		bus = (pbm == &pbm->parent->pbm_B) ? (1 << 4) : 0;

		/* If we have a legal interrupt property, use it as
		 * the IRQ line.
		 */
		if (prom_irq > 0 && prom_irq < 5) {
			line = ((prom_irq - 1) & 3);
		} else {
			u8 pci_irq_line;

			/* Else just directly consult PCI config space. */
			pci_read_config_byte(pdev, PCI_INTERRUPT_PIN, &pci_irq_line);
			line = ((pci_irq_line - 1) & 3);
		}

		/* Now figure out the slot. */
		if (pdev->bus->number == pbm->pci_first_busno) {
			if (pbm == &pbm->parent->pbm_A)
				slot = (pdev->devfn >> 3) - 1;
			else
				slot = (pdev->devfn >> 3) - 2;
		} else {
			if (pbm == &pbm->parent->pbm_A)
				slot = (pdev->bus->self->devfn >> 3) - 1;
			else
				slot = (pdev->bus->self->devfn >> 3) - 2;
		}
		slot = slot << 2;

		pdev->irq = p->irq_build(p, pdev,
					 ((portid << 6) & PCI_IRQ_IGN) |
					 (bus | slot | line));
	}

have_irq:
	pci_write_config_byte(pdev, PCI_INTERRUPT_LINE,
			      pdev->irq & PCI_IRQ_INO);
}

void __init pci_fixup_irq(struct pci_pbm_info *pbm,
			  struct pci_bus *pbus)
{
	struct list_head *walk = &pbus->devices;

	for (walk = walk->next; walk != &pbus->devices; walk = walk->next)
		pdev_fixup_irq(pci_dev_b(walk));

	walk = &pbus->children;
	for (walk = walk->next; walk != &pbus->children; walk = walk->next)
		pci_fixup_irq(pbm, pci_bus_b(walk));
}

#undef DEBUG_BUSMASTERING

static void pdev_setup_busmastering(struct pci_dev *pdev, int is_66mhz)
{
	u16 cmd;
	u8 hdr_type, min_gnt, ltimer;

#ifdef DEBUG_BUSMASTERING
	printk("PCI: Checking DEV(%s), ", pdev->name);
#endif

	pci_read_config_word(pdev, PCI_COMMAND, &cmd);
	cmd |= PCI_COMMAND_MASTER;
	pci_write_config_word(pdev, PCI_COMMAND, cmd);

	/* Read it back, if the mastering bit did not
	 * get set, the device does not support bus
	 * mastering so we have nothing to do here.
	 */
	pci_read_config_word(pdev, PCI_COMMAND, &cmd);
	if ((cmd & PCI_COMMAND_MASTER) == 0) {
#ifdef DEBUG_BUSMASTERING
		printk("no bus mastering...\n");
#endif
		return;
	}

	/* Set correct cache line size, 64-byte on all
	 * Sparc64 PCI systems.  Note that the value is
	 * measured in 32-bit words.
	 */
#ifdef DEBUG_BUSMASTERING
	printk("set cachelinesize, ");
#endif
	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
			      64 / sizeof(u32));

	pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr_type);
	hdr_type &= ~0x80;
	if (hdr_type != PCI_HEADER_TYPE_NORMAL) {
#ifdef DEBUG_BUSMASTERING
		printk("hdr_type=%x, exit\n", hdr_type);
#endif
		return;
	}

	/* If the latency timer is already programmed with a non-zero
	 * value, assume whoever set it (OBP or whoever) knows what
	 * they are doing.
	 */
	pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &ltimer);
	if (ltimer != 0) {
#ifdef DEBUG_BUSMASTERING
		printk("ltimer was %x, exit\n", ltimer);
#endif
		return;
	}

	/* XXX Since I'm tipping off the min grant value to
	 * XXX choose a suitable latency timer value, I also
	 * XXX considered making use of the max latency value
	 * XXX as well.  Unfortunately I've seen too many bogusly
	 * XXX low settings for it to the point where it lacks
	 * XXX any usefulness.  In one case, an ethernet card
	 * XXX claimed a min grant of 10 and a max latency of 5.
	 * XXX Now, if I had two such cards on the same bus I
	 * XXX could not set the desired burst period (calculated
	 * XXX from min grant) without violating the max latency
	 * XXX bound.  Duh...
	 * XXX
	 * XXX I blame dumb PC bios implementors for stuff like
	 * XXX this, most of them don't even try to do something
	 * XXX sensible with latency timer values and just set some
	 * XXX default value (usually 32) into every device.
	 */

	pci_read_config_byte(pdev, PCI_MIN_GNT, &min_gnt);

	if (min_gnt == 0) {
		/* If no min_gnt setting then use a default
		 * value.
		 */
		if (is_66mhz)
			ltimer = 16;
		else
			ltimer = 32;
	} else {
		int shift_factor;

		if (is_66mhz)
			shift_factor = 2;
		else
			shift_factor = 3;

		/* Use a default value when the min_gnt value
		 * is erroneously high.
		 */
		if (((unsigned int) min_gnt << shift_factor) > 512 ||
		    ((min_gnt << shift_factor) & 0xff) == 0) {
			ltimer = 8 << shift_factor;
		} else {
			ltimer = min_gnt << shift_factor;
		}
	}

	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, ltimer);
#ifdef DEBUG_BUSMASTERING
	printk("set ltimer to %x\n", ltimer);
#endif
}

void pci_determine_66mhz_disposition(struct pci_pbm_info *pbm,
				     struct pci_bus *pbus)
{
	struct list_head *walk;
	int all_are_66mhz;
	u16 status;

	if (pbm->is_66mhz_capable == 0) {
		all_are_66mhz = 0;
		goto out;
	}

	walk = &pbus->devices;
	all_are_66mhz = 1;
	for (walk = walk->next; walk != &pbus->devices; walk = walk->next) {
		struct pci_dev *pdev = pci_dev_b(walk);

		pci_read_config_word(pdev, PCI_STATUS, &status);
		if (!(status & PCI_STATUS_66MHZ)) {
			all_are_66mhz = 0;
			break;
		}
	}
out:
	pbm->all_devs_66mhz = all_are_66mhz;

	printk("PCI%d(PBM%c): Bus running at %dMHz\n",
	       pbm->parent->index,
	       (pbm == &pbm->parent->pbm_A) ? 'A' : 'B',
	       (all_are_66mhz ? 66 : 33));
}

void pci_setup_busmastering(struct pci_pbm_info *pbm,
			    struct pci_bus *pbus)
{
	struct list_head *walk = &pbus->devices;
	int is_66mhz;

	is_66mhz = pbm->is_66mhz_capable && pbm->all_devs_66mhz;

	for (walk = walk->next; walk != &pbus->devices; walk = walk->next)
		pdev_setup_busmastering(pci_dev_b(walk), is_66mhz);

	walk = &pbus->children;
	for (walk = walk->next; walk != &pbus->children; walk = walk->next)
		pci_setup_busmastering(pbm, pci_bus_b(walk));
}

/* Generic helper routines for PCI error reporting. */
void pci_scan_for_target_abort(struct pci_controller_info *p,
			       struct pci_pbm_info *pbm,
			       struct pci_bus *pbus)
{
	struct list_head *walk = &pbus->devices;

	for (walk = walk->next; walk != &pbus->devices; walk = walk->next) {
		struct pci_dev *pdev = pci_dev_b(walk);
		u16 status, error_bits;

		pci_read_config_word(pdev, PCI_STATUS, &status);
		error_bits =
			(status & (PCI_STATUS_SIG_TARGET_ABORT |
				   PCI_STATUS_REC_TARGET_ABORT));
		if (error_bits) {
			pci_write_config_word(pdev, PCI_STATUS, error_bits);
			printk("PCI%d(PBM%c): Device [%s] saw Target Abort [%016x]\n",
			       p->index, ((pbm == &p->pbm_A) ? 'A' : 'B'),
			       pdev->name, status);
		}
	}

	walk = &pbus->children;
	for (walk = walk->next; walk != &pbus->children; walk = walk->next)
		pci_scan_for_target_abort(p, pbm, pci_bus_b(walk));
}

void pci_scan_for_master_abort(struct pci_controller_info *p,
			       struct pci_pbm_info *pbm,
			       struct pci_bus *pbus)
{
	struct list_head *walk = &pbus->devices;

	for (walk = walk->next; walk != &pbus->devices; walk = walk->next) {
		struct pci_dev *pdev = pci_dev_b(walk);
		u16 status, error_bits;

		pci_read_config_word(pdev, PCI_STATUS, &status);
		error_bits =
			(status & (PCI_STATUS_REC_MASTER_ABORT));
		if (error_bits) {
			pci_write_config_word(pdev, PCI_STATUS, error_bits);
			printk("PCI%d(PBM%c): Device [%s] received Master Abort [%016x]\n",
			       p->index, ((pbm == &p->pbm_A) ? 'A' : 'B'),
			       pdev->name, status);
		}
	}

	walk = &pbus->children;
	for (walk = walk->next; walk != &pbus->children; walk = walk->next)
		pci_scan_for_master_abort(p, pbm, pci_bus_b(walk));
}

void pci_scan_for_parity_error(struct pci_controller_info *p,
			       struct pci_pbm_info *pbm,
			       struct pci_bus *pbus)
{
	struct list_head *walk = &pbus->devices;

	for (walk = walk->next; walk != &pbus->devices; walk = walk->next) {
		struct pci_dev *pdev = pci_dev_b(walk);
		u16 status, error_bits;

		pci_read_config_word(pdev, PCI_STATUS, &status);
		error_bits =
			(status & (PCI_STATUS_PARITY |
				   PCI_STATUS_DETECTED_PARITY));
		if (error_bits) {
			pci_write_config_word(pdev, PCI_STATUS, error_bits);
			printk("PCI%d(PBM%c): Device [%s] saw Parity Error [%016x]\n",
			       p->index, ((pbm == &p->pbm_A) ? 'A' : 'B'),
			       pdev->name, status);
		}
	}

	walk = &pbus->children;
	for (walk = walk->next; walk != &pbus->children; walk = walk->next)
		pci_scan_for_parity_error(p, pbm, pci_bus_b(walk));
}