📄 wlc.asm
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;tsc.asm ;
;*** Set this variable to '1' for the use on the Simulator ***;SIM .set 0 ;1 = Simulator ;0 = STK/EVK
;RAM_orig .set 00230h ; Free Memory startadress
; .if SIM=0
;USER_END .set 003FFh ; RAM endadress-31 STK/EVK
;counts .set 0FFFFh ; counts for STK/EVK
; .else
;USER_END .set 0FFFFh ; RAM endadress-31 Simulator
;counts .set 0FFh ; Counts for Simulator
; .endif
; Memory Map
RAM_orig .set 00240h ; Start of on-chip RAM (data)
SP_orig .set 003DEh ; User Stack
ROM_orig .set 0C000h ; Start of ROM area (code)upt vector table
USER_END .set 0FFFFh ; End of ROM area, end of interrupt vector table
;--- Control register definitions
IE1 .equ 0h
IE2 .equ 01h
IFG1 .equ 02h
IFG2 .equ 03h
ME1 .equ 04h
ME2 .equ 05h
P0IN .equ 010h
P0OUT .equ 011h
P0DIR .equ 012h
P0IFG .equ 013h
P0IES .equ 014h
P0IE .equ 015h
P0IN0 .set 001h
LCDM .equ 030h
LCD1 .equ 031h
BTME .set 080h ; BT module enable
BTIE .set 080h ; BT intrpt enable
BTIFG .equ 080h ; BT intrpt flag
P0IE0 .set 004h ; P0.0 intrpt enable
P0IFG0 .set 004h ; P0.0 intrpt flag
P0DIR0 .set 001h ; P0.0 direction
P0IES0 .set 001h ; P0.0 edge select
BTCTL .equ 040h ; BT control
TCCTL .equ 042h ; Address of Timer/Counter control register
TCPLD .equ 043h ; Address of Timer/Counter pre-load register
TCDAT .equ 044h ; Address of Timer/Counter
SCFI0 .equ 050h
SCFI1 .equ 051h
SCFQCTL .equ 052h
WDTCTL .equ 0120h
WDTHold .equ 80h
WDT_wrkey .equ 05A00h
GIE .equ 08h
TPD .equ 04Eh
TPE .equ 04Fh
; Hardware Definitions for the ADC
AIN .equ 0110h ; Input Register (For Digital Inputs)
AEN .equ 0112h ; 0: Analog Input 1: Digital Input
ACTL .equ 0114h ; ADC Control Register
ADAT .equ 0118h ; ADC Data Register (12 or 14 bit)
ADIFG .equ 04h ; ADC End-of-Conversion Bit (IFG2.2)
ADIE .equ 02h ; ADC Interrupt Enable Bit
CS .equ 01h ; Conversion Start
VREF .equ 02h ; 0: Ext. Reference 1: SVCC On
A0 .equ 00h ; Input A0
A1 .equ 04h ; Input A1
A2 .equ 08h ; Input A2
CSA0 .equ 00h ; Current Source to A0
CSA1 .equ 40h ; Current Source to A1
CSOFF .equ 100h ; Current Source Off
CSON .equ 000h ; Current Source On
RNGA .equ 00h ; Range Select (0 ... 0.25SVCC)
RNGB .equ 200h ; Range Select (0.25 ... 0.50SVCC)
RNGC .equ 400h ; Range Select (0.50 ... 0.75SVCC)
RNGD .equ 600h ; Range Select (0.75 ... SVCC)
RNGAUTO .equ 800h ; 1: Range Selected Automatically
PD .equ 1000h ; 1: ADC Powered Down
; Address Definitions
MON_TIMER_VECTOR .equ 03E2h
; Defines
strap_cycles .equ 100
radio_cycles .equ 100
radio_spin_time .equ 20000
upper_trigger_offset .equ 25l
lower_trigger_offset .equ 25
upper_noise_offset .equ 10
lower_noise_offset .equ 10
magic_1 .equ 'P'
magic_2 .equ 'F'
zero_timeout .equ 50
not_triggered .equ 0
waiting_for_dip .equ 1
waiting_for_rise .equ 2
triggered_on_dip .equ 3
triggered_on_rise .equ 4
;; Port 0
CHAN_A_POWER .equ 00000001b
CHAN_B_POWER .equ 00001000b
STRAP_SET .equ 00010000b
STRAP_RESET .equ 00100000b
OFFSET_1 .equ 01000000b
OFFSET_2 .equ 10000000b
;; Port TC
CHSEL0 .equ 00000001b
CHSEL1 .equ 00000010b
CHSEL2 .equ 00000100b
RADIO_POWER .equ 00001000b
DATA .equ 00010000b
TEMP_POWER .equ 00100000b
;; Analog Inputs
CHAN_A_OUT .equ A1
CHAN_B_OUT .equ A0
TEMP_OUT .equ A2
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *; Variable Declarations; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
.sect "Data", RAM_orig.data
;; Words
.bss baseline_counter, 2, 0200h
.bss radio_counter, 2
.bss trigger_upper,2
.bss trigger_lower,2
.bss zerocount, 2
.bss noise_upper, 2
.bss noise_lower, 2
.bss baseline, 2
.bss baseline_acc, 2
.bss temperature, 2
.bss vehicle_count, 2
;; Bytes
.bss strap_counter, 1
.bss trigger_state, 1
.bss checksum, 1
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *; Interrupt vectors; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
.sect "Int_Vect",USER_END-31
.word RESET
.word timer_handler ; Basic Timer Interrupt
.word RESET
.word RESET
.word RESET
.word RESET
.word RESET
.word RESET
.word RESET
.word RESET
.word RESET
.word RESET
.word RESET
.word RESET
.word RESET
.word RESET ; POR, ext. Reset, Watchdog
.end
;************************************************************************; Reset : Initialize processor;************************************************************************
.sect "MAIN",ROM_origRESET
MOV #SP_orig,SP ; initialize stackpointer
MOV #(WDTHold+WDT_wrkey),&WDTCTL ; Stop Watchdog Timer
;; Setup Basic Timer 0;; This is the main system timebase. It generates interrupts at 128 Hz. 7.8ms
;; Input Select = ACLK
;; Hold = 0 (?)
;; Input Divide = 1
;; LCD Frequency = ACLK/256
;; Interrupt Frequency = Fclk2/256
MOV.B #00011111b, BTCTL
;; Initialize port pins
BIS.B #11111001b,&P0DIR ; Setup Port 0 direction
BIC.W #00FFh, &AEN ; All Port A pins are analog inputs
BIS.B #00111111b, &TPE ; All Timer/Port TP pins are outputs
;; Set default values for port pins -- everything powered down
BIS.B #(CHAN_A_POWER|CHAN_B_POWER|STRAP_SET|STRAP_RESET|OFFSET_1|OFFSET_2),&P0OUT
MOV.B #RADIO_POWER, &TPD
;; Initalize Variables
MOV.W #1000, baseline_counter
MOV.W #0, vehicle_count
MOV.B #not_triggered, trigger_state
MOV.W #zero_timeout, zerocount
MOV.W #2000, baseline
MOV.W #2000, baseline_acc
MOV.B #strap_cycles, strap_counter
MOV.W #radio_cycles, radio_counter
;--- Enable Interrupts
MOV.B #0h,IE1
MOV.B #10000000b, IE2 ; Enable Basic Timer Interrupt
CLR.B IFG1
CLR.B IFG2
;--- Global Interrupt Enable
BIS.W #0000000000001000b, SR
;******************************************************************************; Main Loop ;******************************************************************************mainloop nop
jmp mainloop
;******************************************************************************; Basic Timer 0 Interrupt Service Routine ;******************************************************************************timer_handler:
;; First, we acquire data from the sensor.
;; The A/D conversion starts by holding the sampling gate
;; open for 12 cycles. However, the passband of the RC filter that
;; causes the settling time of the ADC SHA cap is much larger than
;; the passband of the instrumentation amplifier---so we only need
;; to make sure that a valid signal is present at the sampling gate
;; when it is closed.
;; This code leaves the sensor and amplifiers on for
;; 6.4 us. The sampling gate closes just as the
;; sensor is being turned off, but the system is
;; synchronous, so this is fine. You can see the sampling
;; gate opening on the scope, since nothing is driving the
;; sensor then. The sampling gate closes 12 us later.
;; Start A/D Conversion 12us + 84us=96us
MOV #RNGA+CSOFF+CHAN_A_OUT+VREF+CS, &ACTL
NOP
NOP
;; Power up sensors
BIC.B #(CHAN_A_POWER),&P0OUT
NOP
NOP
NOP
NOP ; extra
;; Power down sensors
BIS.B #(CHAN_A_POWER),&P0OUT
;; Spin wait for conversion to finish (change!)
waiting BIT.B #ADIFG, &IFG2 ;;A/D conversion
JZ waiting
;; Reset the flag to zero so it can trip next time
BIC.B #ADIFG, &IFG2
MOV &ADAT, R9
call #vehicle_detector
; Strap the sensor every 100 cycles
DEC.B strap_counterJZ strap
; Run the radio every 500 cycles
DEC.W radio_counterJZ radio
finished:
RETI
strap:
MOV.B #strap_cycles, strap_counter
BIC.B #(STRAP_RESET), &P0OUT ;; .not.src.and.dst -> dst; Wait 1 us BIC.B #(STRAP_SET), &P0OUT; Wait 5 us NOP NOP NOP BIS.B #(STRAP_SET), &P0OUT ;; Src.or.dst -> dst; Wait 20 us MOV.B #5, R6
dels:
DEC.B R6 JNZ dels BIS.B #(STRAP_RESET), &P0OUT
JMP finished
radio:
MOV.W #radio_cycles, radio_counter ;; power up radio and temp sensor MOV.B #(5|DATA|TEMP_POWER), &TPD ;Set radio for 915.37 MHz ⌨️ 快捷键说明
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