orcomp.vhd

介绍数字滤波器的设计

		trise_clk_q : time := 1 ns; 
		tfall_clk_q : time := 1 ns
		);
PORT (q : OUT std_logic := '0';
 	qNot : OUT std_logic;
 	d : IN std_logic;
 	clk : std_logic
 	);
END orcad_dff;

ARCHITECTURE model OF orcad_dff IS
BEGIN

PROCESS (clk)
BEGIN

	IF (clk = '1') AND clk'EVENT THEN
		IF d = '0' THEN
                q <= '0' AFTER tfall_clk_q;
                qNot <= '1' AFTER tfall_clk_q;
		ELSIF d = '1' THEN
                q <= '1' AFTER trise_clk_q;
                qNot <= '0' AFTER trise_clk_q;
        ELSE
                q <= TO_X01(d) AFTER trise_clk_q;
                qNot <= NOT TO_X01(d) AFTER trise_clk_q;
        END IF;
	END IF;

END PROCESS;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY orcad_dqffpc IS
GENERIC (
		trise_clk_q : time := 1 ns; 
		tfall_clk_q : time := 1 ns
		);
PORT (q : OUT std_logic;
 	d : IN std_logic;
 	clk : std_logic;
 	cl : std_logic;
 	pr : std_logic
 	);
END orcad_dqffpc;

ARCHITECTURE model OF orcad_dqffpc IS
BEGIN

PROCESS (cl, clk, pr)
BEGIN

	IF(cl = '0') THEN
		q <= '0' AFTER tfall_clk_q;

	ELSIF (pr = '0') THEN
		q <= '1' AFTER trise_clk_q;

	ELSIF (clk = '1') AND clk'EVENT THEN
		IF d = '0' THEN
                q <= '0' AFTER tfall_clk_q;
		ELSIF d = '1' THEN
                q <= '1' AFTER trise_clk_q;
        ELSE
                q <= TO_X01(d) AFTER trise_clk_q;
        END IF;
	END IF;

END PROCESS;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY orcad_dffpc IS
GENERIC (
		trise_clk_q : time := 1 ns; 
		tfall_clk_q : time := 1 ns
		);
PORT (q : OUT std_logic;
 	qNot : OUT std_logic;
 	d : IN std_logic;
 	clk : std_logic;
 	cl : std_logic;
 	pr : std_logic
 	);
END orcad_dffpc;

ARCHITECTURE model OF orcad_dffpc IS
BEGIN

PROCESS (cl, clk, pr)
BEGIN

	IF(cl = '0') THEN
		q <= '0' AFTER tfall_clk_q;
		qNot <= '1' AFTER tfall_clk_q;

	ELSIF (pr = '0') THEN
		q <= '1' AFTER trise_clk_q;
		qNot <= '0' AFTER trise_clk_q;

	ELSIF (clk = '1') AND clk'EVENT THEN
		IF d = '0' THEN
                q <= '0' AFTER tfall_clk_q;
                qNot <= '1' AFTER tfall_clk_q;
		ELSIF d = '1' THEN
                q <= '1' AFTER trise_clk_q;
                qNot <= '0' AFTER trise_clk_q;
        ELSE
                q <= TO_X01(d) AFTER trise_clk_q;
                qNot <= NOT TO_X01(d) AFTER trise_clk_q;
        END IF;
	END IF;

END PROCESS;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY orcad_jkffc IS
GENERIC (
		trise_clk_q : time := 1 ns; 
		tfall_clk_q : time := 1 ns
		);
PORT (q : OUT std_logic;
 	qNot : OUT std_logic;
 	j : IN std_logic;
 	k : IN std_logic;
 	clk : IN std_logic;
 	cl : IN std_logic
 	);
END orcad_jkffc;

ARCHITECTURE model OF orcad_jkffc IS
SIGNAL N1  : std_logic;
SIGNAL N1N : std_logic;

BEGIN

PROCESS (cl, clk)
BEGIN

	IF(cl = '0') THEN
		N1 <= '0';
		N1N <= '1';

	ELSIF (clk = '1') AND clk'EVENT THEN
		IF (j = '1') AND (k = '1') THEN
					 N1 <= NOT N1;
					 N1N <= NOT N1N;
		ELSIF k = '1' THEN
                N1 <= '0';
                N1N <= '1';
		ELSIF j = '1' THEN
                N1 <= '1';
                N1N <= '0';
         END IF;
	END IF;
END PROCESS;
q    <= N1 AFTER trise_clk_q;
qNot <= N1N AFTER trise_clk_q;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY orcad_jkffp IS
GENERIC (
		trise_clk_q : time := 1 ns; 
		tfall_clk_q : time := 1 ns
		);
PORT (q : OUT std_logic;
 	qNot : OUT std_logic;
 	j : IN std_logic;
 	k : IN std_logic;
 	clk : IN std_logic;
 	pr : IN std_logic
 	);
END orcad_jkffp;

ARCHITECTURE model OF orcad_jkffp IS
SIGNAL N1  : std_logic;
SIGNAL N1N : std_logic;

BEGIN

PROCESS (clk, pr)
BEGIN

	IF(pr = '0') THEN
		N1  <= '1';
		N1N <= '0';

	ELSIF (clk = '1') AND clk'EVENT THEN
		IF (j = '1') AND (k = '1') THEN
					 N1  <= NOT N1;
					 N1N <= NOT N1N;
		ELSIF k = '1' THEN
                N1  <= '0';
                N1N <= '1';
		ELSIF j = '1' THEN
                N1  <= '1';
                N1N <= '0';
         END IF;
	END IF;

END PROCESS;
q <= N1 AFTER trise_clk_q;
qNot <= N1N AFTER trise_clk_q;

END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY orcad_jkffpc IS
GENERIC (
		trise_clk_q : time := 1 ns; 
		tfall_clk_q : time := 1 ns
		);
PORT (q : OUT std_logic;
 	qNot : OUT std_logic;
 	j : IN std_logic;
 	k : IN std_logic;
 	clk : IN std_logic;
 	cl : IN std_logic;
 	pr : IN std_logic
 	);
END orcad_jkffpc;

ARCHITECTURE model OF orcad_jkffpc IS
SIGNAL N1  : std_logic;
SIGNAL N1N : std_logic;

BEGIN

PROCESS (cl, clk, pr)
BEGIN

	IF(cl = '0') THEN
		N1  <= '0';
		N1N <= '1';

	ELSIF (pr = '0') THEN
		N1  <= '1';
		N1N <= '0';
		
	ELSIF (clk = '1') AND clk'EVENT THEN
		IF (j = '1') AND (k = '1') THEN
					 N1  <= NOT N1;
					 N1N <= NOT N1N;
		ELSIF k = '1' THEN
                N1  <= '0';
                N1N <= '1';
		ELSIF j = '1' THEN
                N1  <= '1';
                N1N <= '0';
         END IF;
	END IF;

END PROCESS;
q    <= N1  AFTER trise_clk_q;
qNot <= N1N AFTER trise_clk_q;

END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;


ENTITY orcad_dlatch IS
GENERIC (
		trise_clk_q : time := 1 ns; 
		tfall_clk_q : time := 1 ns
		);
PORT (q : OUT std_logic := '0';
 	d : IN std_logic;
 	enable : std_logic
 	);
END orcad_dlatch;

ARCHITECTURE model OF orcad_dlatch IS
BEGIN

PROCESS (d, enable)
BEGIN

	IF (enable = '1') THEN
		IF d = '0' THEN
                q <= '0' AFTER tfall_clk_q;
		ELSIF d = '1' THEN
                q <= '1' AFTER trise_clk_q;
         END IF;
	END IF;

END PROCESS;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY orcad_dlatchpc IS
GENERIC (
		trise_clk_q : time := 1 ns; 
		tfall_clk_q : time := 1 ns
		);
PORT (q : OUT std_logic := '0';
 	d : IN std_logic;
 	enable : std_logic;
 	cl : std_logic;
 	pr : std_logic
 	);
END orcad_dlatchpc;

ARCHITECTURE model OF orcad_dlatchpc IS
BEGIN

PROCESS (d, cl, enable, pr)
BEGIN

	IF(cl = '0') THEN
		q <= '0' AFTER tfall_clk_q;

	ELSIF (pr = '0') THEN
		q <= '1' AFTER trise_clk_q;

	ELSIF (enable = '1') THEN
		IF d = '0' THEN
                q <= '0' AFTER tfall_clk_q;
		ELSIF d = '1' THEN
                q <= '1' AFTER trise_clk_q;
         END IF;
	END IF;

END PROCESS;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY orcad_itsb IS
GENERIC (
		trise_i1_o : time := 1 ns; 
		tfall_i1_o : time := 1 ns;
		tpd_en_o : time := 1 ns
		);
PORT (o : OUT std_logic;
 	i1 : IN std_logic;
 	en : std_logic
 	);
END orcad_itsb;

ARCHITECTURE model OF orcad_itsb IS
BEGIN

PROCESS (i1, en)
BEGIN
	IF (en = '0') THEN o <= 'Z' AFTER tpd_en_o;
	ELSE
		IF i1 = '1' THEN
                o <= '0' AFTER tfall_i1_o;
		ELSIF i1 = '0' THEN
                o <= '1' AFTER trise_i1_o;
		ELSE
			  o <= TO_X01(i1);
         END IF;
	END IF;
END PROCESS;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;


ENTITY orcad_tsb IS
GENERIC (
		trise_i1_o : time := 1 ns; 
		tfall_i1_o : time := 1 ns;
		tpd_en_o : time := 1 ns
		);
PORT (o : OUT std_logic;
 	i1 : IN std_logic;
 	en : std_logic
 	);
END orcad_tsb;

ARCHITECTURE model OF orcad_tsb IS
BEGIN

PROCESS (i1, en)
BEGIN
	IF (en = '0') THEN o <= 'Z' AFTER tpd_en_o;
	ELSE
		IF i1 = '1' THEN
                o <= '1' AFTER tfall_i1_o;
		ELSIF i1 = '0' THEN
                o <= '0' AFTER trise_i1_o;
		ELSE
			  o <= TO_X01(i1);
         END IF;
	END IF;
END PROCESS;
END model;